10.2. Cortex-M7 CTI functional description

The Cortex-M7 CTI is connected to a number of trigger inputs and trigger outputs. Figure 10.1 shows the debug system components and the available trigger inputs and trigger outputs.

Figure 10.1. Debug system components

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Table 10.1 shows how the CTI trigger inputs are connected to the Cortex-M7 processor.

Table 10.1. Trigger signals to the CTI

SignalDescriptionConnectionAcknowledge, handshake
CTITRIGIN[7]ETM Event Output 3ETM to CTIPulsed
CTITRIGIN[6]ETM Event Output 2
CTITRIGIN[5]ETM Event Output 1
CTITRIGIN[4]ETM Event Output 0
CTITRIGIN[3]DWT Comparator Output 2Processor to CTI
CTITRIGIN[2]DWT Comparator Output 1
CTITRIGIN[1]DWT Comparator Output 0
CTITRIGIN[0]Processor Halted

Table 10.2 shows how the CTI trigger outputs are connected to the processor and ETM.

Table 10.2. Trigger signals from the CTI

SignalDescriptionConnectionAcknowledge, handshake
CTITRIGOUT[7]Processor RestartCTI to ProcessorProcessor Restarted
CTITRIGOUT[6]ETM Event Input 3 CTI to ETMPulsed
CTITRIGOUT[5]ETM Event Input 2Pulsed
CTITRIGOUT[4]ETM Event Input 1Pulsed
CTITRIGOUT[3]ETM Event Input 0Pulsed
CTITRIGOUT[2]Interrupt request 1 CTI to systemAcknowledged by writing to the CTIINTACK register in ISR
CTITRIGOUT[1]Interrupt request 0
CTITRIGOUT[0]Processor debug requestCTI to processorAcknowledged by the debugger writing to the CTIINTACK register

Note

  • After the processor is halted using CTI Trigger Output 0, the Processor Debug Request signal remains asserted. The debugger must write to CTIINTACK to clear the halting request before restarting the processor.

  • After asserting an interrupt using the CTI Trigger Output 1 or 2, the Interrupt Service Routine (ISR) must clear the interrupt request by writing to the CTI Interrupt Acknowledge, CTIINTACK.

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