5.6.2. AHBP semaphores

The peripheral interfaces use the internal exclusive monitor of the memory system to manage load, store and clear exclusive instructions to non-shared memory. The internal monitor checks exclusive accesses to shared memory and also, if necessary, any external monitor using the AHB memory interface. You can use these instructions to construct semaphores and ensure synchronization between different processes or processors. See the Arm®v7-M Architecture Reference Manual for more information about how these instructions work.

Only exclusive instructions to shared memory result in exclusive accesses on the AHBP. Exclusive accesses to non-shared memory are marked as non-exclusive accesses on the bus.

The AHBP extension signals EXREQP and EXRESPP signal exclusive request and response for shared exclusive transactions on AHBP.

AHBP exclusive accesses

This section describes the EXREQP and EXRESPP signals and the transaction properties for AHBP exclusive accesses:

  • EXREQP is an address phase signal and is only asserted when HTRANSP indicates a valid transaction.

  • EXRESPP is a data phase signal and is only sampled on a data phase when HREADYP is 1.

The processor only asserts the EXREQP signal when:

  • A load exclusive is performed to a Shared memory region on the AHBP.

  • A store exclusive is performed to a Shared memory region on the AHBP and the internal exclusive access monitor passes. When the internal exclusive access monitor fails, no store is performed on the AHBP.

Table 5.36 shows the transaction properties the system must use for EXRESPP.

Table 5.36. Transaction properties

Transaction propertiesRequired EXRESPP
EXREQPLoad/Store

0

Load/Store

-
1

Load

0 if a system monitor is implemented that covers the access address

1 otherwise

1

Store

1 if a system monitor is implemented that covers the access address and the exclusive check fails

0 otherwise


Software must avoid performing exclusive accesses to shared regions of memory if no global exclusive monitor is implemented that covers the region in question. The processor treats such accesses as an error condition and automatically takes a BusFault exception if a load is performed with EXREQP set to 1 and receives EXRESPP set to 1. The processor ignores EXRESPP for accesses that:

  • Are performed with EXREQP set to 0. Arm recommends that the system drives EXRESPP to 0 in these cases.

  • Return an error response on HRESPP.

The Cortex-M7 processor uses EXREQP and EXRESPP differently from the Cortex-M3 processor and the Cortex-M4 processor, therefore you might have to update both system hardware and software when moving to a system using the Cortex-M7 processor.

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