3.3.3. Cache Level ID Register

The CLIDR Register characteristics are:

Purpose
  • Indicates the cache levels that are implemented. Architecturally, there can be a different number of cache levels on the instruction and data side.

  • Captures the point-of-coherency.

  • Captures the point-of-unification.

Usage constraints

The CLIDR is:

  • A read-only register.

  • Accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See the register summary in Table 3.5.

Figure 3.3 shows the CLIDR bit assignments.

Figure 3.3.  CLIDR bit assignments

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Table 3.5 shows the CLIDR bit assignments.

Table 3.5. CLIDR bit assignments

BitsNameFunction
[31:30]-Reserved.
[29:27]LoUU

Level of Unification Uniprocessor:

0b001

Level 2, if either cache is implemented.

0b000

Level 1, if neither instruction nor data cache is implemented.

[26:24]LoC

Level of Coherency:

0b001

Level 2, if either cache is implemented.

0b000

Level 1, if neither instruction nor data cache is implemented.

[23:3]-Reserved.
[2:0]Ctype1

Level 1 cache type:

0b000

No instruction or data cache is implemented.

0b001

Instruction cache is implemented.

0b010

Data cache is implemented.

0b011

Instruction and data cache are implemented.


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