3.3.5. Cache Size Selection Register

The CSSELR characteristics are:

Purpose

Holds the value that the processor uses to select the CSSELR to use.

Usage constraints

The CSSELR is:

  • A read/write register.

  • Accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See the register summary in Table 3.8.

Figure 3.5 shows the CSSELR bit assignments.

Figure 3.5.  CSSELR bit assignments

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Table 3.8 shows the CSSELR bit assignments.

Table 3.8. CSSELR bit assignments

Bits

NameFunction
[31:4]-Reserved.
[3:1]Level

Identifies which cache level to select.

0b000

Level 1 cache.

This field is RAZ/WI.

[0]InD

Selects either instruction or data cache.

0

Data cache.

1

Instruction cache.


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