3.3.4. Cache Size ID Register

The CCSIDR characteristics are:

Purpose

Provides information about the size and behavior of the instruction or data cache selected by the CSSELR. Architecturally, there can be up to eight levels of cache, containing instruction, data, or unified caches. This processor contains L1 instruction and data caches only.

Usage constraints

The CCSIDR is:

  • A read-only register.

  • Accessible in Privileged mode only.

Configurations

Available in all processor configurations.

If no instruction or data cache is configured, the corresponding CCSIDR is RAZ.

Attributes

See the register summary in Table 3.6.

Figure 3.4 shows the CCSIDR bit assignments.

Figure 3.4.  CCSIDR bit assignments

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Table 3.6 shows the CCSIDR bit assignments.

Table 3.6. CCSIDR bit assignments

Bits

Name Function[a]
[31]WT

Indicates support available for Write-Through:

1

Write-Through support available.

[30]WB

Indicates support available for Write-Back:

1

Write-Back support available.

[29]RA

Indicates support available for read allocation:

1

Read allocation support available.

[28]WA

Indicates support available for write allocation:

1

Write allocation support available.

[27:13]NumSets

Indicates the number of sets as:

(number of sets) - 1.

Cache-size dependent.

[12:3]Associativity

Indicates the number of ways as:

(number of ways) - 1.

0x1

Represents two ways.

0x3

Represents four data ways.

[2:0]LineSize

Indicates the number of words in each cache line.

0x1

Represents 32 bytes.

[a] See Table 3.7 for valid bit field encodings.


The LineSize field is encoded as 2 less than log(2) of the number of words in the cache line. For example, a value of 0x0 indicates there are four words in a cache line, that is the minimum size for the cache. A value of 0x1 indicates there are eight words in a cache line.

Table 3.7 shows the individual bit field and complete register encodings for the CCSIDR. Use this to determine the cache size for the L1 data or instruction cache selected by the Cache Size Selection Register (CSSELR). See Cache Size Selection Register.

Table 3.7. CCSIDR encodings

CSSELRCacheSizeComplete register encodingRegister bit field encoding
WTWBRAWANumSetsAssociativity LineSize
0x0Data cache4KB0xF003E01911110x001F0x30x1
8KB0xF007E0190x003F
16KB0xF00FE0190x007F
32KB0xF01FE0190x00FF
64KB0xF03FE0190x01FF
0x1Instruction cache4KB0xF007E00911110x003F0x10x1
8KB0xF00FE0090x007F
16KB0xF01FE0090x00FF
32KB0xF03FE0090x01FF
64KB0xF07FE0090x03FF

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