Appendix A. Revisions

This appendix describes the technical changes between released issues of this book.

Table A.1. Issue A


First release


Table A.2. Differences between issue A and issue B

Arm®v7-M Architecture Reference Manual, issue E.b, defines Flash Patch Breakpoint version 2Arm architecturer0p2 onwards
Prefix CM7_ added to register names ITCMCR, DTCMCR, CACR, AHBSCR, ABFSR and AHBPCR-r0p2
Cortex-M7 processor features clarifiedFeaturesAll revisions
Implementation options table updatedTable 1.1All revisions
Data Process Unit changed to Data Processing UnitData Processing UnitAll revisions
Single MAC pipeline description clarifiedData Processing UnitAll revisions
Prefetch Unit features clarifiedPrefetch UnitAll revisions
ETM block description clarifiedCross Trigger Interface UnitAll revisions
TCM interface description clarifiedTCM interfaceAll revisions
MBIST interface description clarifiedMBIST interfaceAll revisions
Binary compatibility with other Cortex processors section updatedBinary compatibility with other Cortex processorsAll revisions
Exclusive monitor description clarifiedExclusive monitorAll revisions
Private peripheral bus section updatedPrivate peripheral busAll revisions
Exception handling section updatedException handlingAll revisions
System control registers table updatedTable 3.1r0p2
Added ACTLR field descriptions for new system dependent optimization modesAuxiliary Control Registerr0p2
CPUID.REVISION function updatedTable 3.4r0p2
CLIDR bit assignments table updatedTable 3.5r0p2
CCSIDR bit assignments figure clarifiedFigure 3.4All revisions
CCSIDR.Associativity function updatedTable 3.6r0p2
AHBP Control Register clarifiedAHBP Control RegisterAll revisions
CACR[1] name and function updatedTable 3.11r0p2
CACR[0] function updatedTable 3.11All revisions
Changed RAZ to RAO in NoteAbout InitializationAll revisions
Note clarifiedPreloading TCMAll revisions
Changed AHBP peripheral interface to AHBP interfaceAbout the memory systemAll revisions
Changed AHBP peripheral port to AHBP portFault handlingAll revisions
Write ID capability description clarifiedTable 5.3All revisions
ARADDR value for address 0x1D updatedTable 5.20All revisions
TCM attributes and permissions section updatedTCM attributes and permissionsr0p1 and r0p2
Store buffer behavior clarifiedStore bufferAll revisions
Low power modes section updatedLow power modesAll revisions
Processor ROM table identification values addresses updatedTable 9.1All revisions
Processor ROM table components table updatedTable 9.2All revisions
FPB register summary table updatedTable 9.7All revisions
DWT register summary table updatedTable 11.1All revisions
Error bank register behavior section addedProtection methodAll revisions

Table A.3. Differences between issue B and issue C

Bullet list updatedAbout the Cortex-M7 processorr1p0
Features updatedFeaturesr1p0
Memory system section updatedMemory Systemr1p0
Store Buffer section addedStore BufferAll revisions
CPUID reset value updatedTable 3.1r1p0
ACTLR bit functions updatedTable 3.3All revisions
CPUID.VARIANT and CPUID.REVISION functions updatedTable 3.4r1p0
CSSELR bit assignments table updatedTable 3.8All revisions
AHB slave interface section updatedAHB slave interfacer1p0
Memory map section addedMemory mapr1p0
Restrictions on AHBS transactions section updatedRestrictions on AHBS transactionsr1p0
AHBS interface arbitration section updatedAHBS interface arbitrationr1p0
TCM interfaces section updatedTCM interfacesr1p0
Note addedTCM attributes and permissionsr1p0
TCM configuration section updatedTCM configurationr1p0
TCM arbitration section updatedTCM arbitrationr1p0
TCM interface protocol section updatedTCM interface protocolr1p0
TCM read modify write section addedTCM read modify writer1p0
Booting from TCM section addedBooting from TCMr1p0
Integration with Flash memory section addedIntegration with Flash memoryr1p0
System access to TCM section addedSystem access to TCMr1p0

Table A.4. Differences between issue C and issue D


Updated note about the Arm architecture interworking model

ExceptionsAll revisions
CPUID.VARIANT and CPUID.REVISION functions updatedTable 3.1r1p1
Added a note to the CPUID register descriptionCPUID Base RegisterAll revisions
Invalidate the entire data cache description updatedInitializing and enabling the L1 cacheAll revisions

Table A.5. Differences between issue D and issue E

Diagram updatedFigure 1.2r1p1
Diagram updatedFigure 1.3r1p1
Trace stalling information addedETMAll revisions
ITCM, DTCM and AHBP base addresses addedTable 2.1All revisions
Table updatedTable 3.3r1p1
Memory ordering restrictions note addedAbout the memory systemr1p1
Initializing TCMs with ECC note addedTCM read modify writeAll revisions
New chapter Cortex-M7 Trace Port Interface Unit addedChapter 13 Cortex-M7 Trace Port Interface Unitr1p1
Table updatedTable 13.1r1p1

Table A.6. Differences between issue E and issue F

New sections added.Speculative accessesr1p2
AXI transactions generated for Strongly-ordered or Device memory updated. Identifiers for AXIM interface accessesr1p2
Added note. TCM interfacesr1p2
Added note. TCM configurationr1p2
CPUID reset value updated.Table 3.1r1p2

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