1.1. About the Cortex-M7 processor

The Cortex-M7 processor is a highly efficient high-performance, embedded processor that features low interrupt latency, low-cost debug, and has backwards compatibility with existing Cortex-M profile processors. The processor has an in-order super-scalar pipeline that means many instructions can be dual-issued, including load/load and load/store instruction pairs because of multiple memory interfaces.

Memory interfaces that the processor supports include:

The processor has an optional Memory Protection Unit (MPU) that can be configured to protect regions of memory. Error Correcting Code (ECC) functionality for error detection and correction, is included in the data and instruction caches when implemented. The TCM interfaces support the implementation of external ECC to provide improved reliability and to address safety-related applications.

The Cortex-M7 processor includes optional floating-point arithmetic functionality, with support for single and double-precision arithmetic. See Chapter 8 Floating Point Unit.

The processor is intended for high-performance, deeply embedded applications that require fast interrupt response features.

Figure 1.1 shows the processor in a typical system.

Figure 1.1. Example Cortex-M7 system

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