5.5.7. AXIM interface transfers

The processor conforms to the Arm® AMBA® AXI and ACE Protocol Specification, but it does not generate all the AXI transaction types that the specification permits. This section describes the types of AXI transaction that the AXIM interface does not generate.

If you are designing an AXI slave to work only with the Cortex-M7 processor, and there are no other AXI masters in your system, you can take advantage of these restrictions and the interface attributes, described in Table 5.3, to simplify the slave.

This section also contains tables that show some examples of the types of AXI burst that the processor generates. However, because a particular type of transaction is not shown here does not mean that the processor does not generate such a transaction.

Note

An AXI slave device connected to the AXIM interface must be capable of handling every kind of transaction permitted by the Arm® AMBA® AXI and ACE Protocol Specification, except where there is an explicit statement in this chapter that such a transaction is not generated. You must not infer any additional restrictions from the example tables given.

Load and store instructions to Non-cacheable memory might not result in an AXI transfer because the data might either be retrieved from, or merged into the internal store data buffers. The exceptions to this are loads or stores to Strongly-ordered or Device memory. These always result in AXI transfers. See Strongly-ordered and Device transactions.

Restrictions on AXI transfers describes restrictions on the type of transfers that the AXIM interface generates. If the processor is powered up, the buffered write response and read data channel ready signals, BREADY and RREADY, are always asserted. They are deasserted when the processor enters Dormant or Shutdown mode. You must not make any other assumptions about the AXI handshaking signals, except that they conform to the Arm® AMBA® AXI and ACE Protocol Specification.

The following sections give examples of transfers generated by the AXIM interface:

Restrictions on AXI transfers

The AXIM interface applies the following restrictions to the AXI transactions it generates:

  • A burst never transfers more than 32 bytes.

  • The burst length is never more than four transfers.

  • The maximum length of a Strongly-ordered or Device write burst is two transfers. Strongly-ordered or Device reads are always one transfer.

  • No transaction ever crosses a 32-byte boundary in memory. See AXI transaction splitting.

  • FIXED bursts are never used.

  • The write address channel always issues INCR type bursts, and never WRAP or FIXED.

  • WRAP type read bursts, see Linefills:

    • Are used only for linefills (reads) of cacheable Normal memory.

    • Always have a size of 64 bits, and a length of four transfers.

    • Always have a start address that is 64-bit aligned.

  • If the transfer size is 8 bits or 16 bits then the burst length is always one transfer.

  • The transfer size is never greater than 64 bits, because it is a 64-bit AXI bus.

  • Instruction fetches, identified by ARPROT[2], are always a 64 bit transfer size, and never locked or exclusive.

  • Transactions to Device and Strongly-ordered memory are always to addresses that are aligned for the transfer size. See Strongly-ordered and Device transactions.

  • Exclusive accesses are always to addresses that are aligned for the transfer size.

  • Only exclusive accesses to shared memory result in exclusive accesses on the AXIM, identified by ARLOCK and AWLOCK. Exclusive accesses to non-shared memory are marked as non-exclusive accesses on the bus.

Strongly-ordered and Device transactions

A load or store instruction to or from Strongly-ordered or Device memory always generates AXI transactions of the same size as implied by the instruction. All accesses using LDM, STM, LDRD, or STRD instructions to Strongly-ordered or Device memory occur as 32-bit transfers.

LDRB

Table 5.6 shows the values of ARADDR, ARBURST, ARSIZE, and ARLEN for a LDRB from bytes 0-7 in Strongly-ordered or Device memory.

Table 5.6. LDRB from Strongly-ordered or Device

Address[2:0]ARADDRARBURSTARSIZEARLEN
0x0 (byte 0)0x00Incr8-bit1 data transfer
0x1 (byte 1)0x01Incr8-bit1 data transfer
0x2 (byte 2)0x02Incr8-bit1 data transfer
0x3 (byte 3)0x03Incr8-bit1 data transfer
0x4 (byte 4)0x04Incr8-bit1 data transfer
0x5 (byte 5)0x05Incr8-bit1 data transfer
0x6 (byte 6)0x06Incr8-bit1 data transfer
0x7 (byte 7)0x07Incr8-bit1 data transfer

LDRH

Table 5.7 shows the values of ARADDR, ARBURST, ARSIZE, and ARLEN for a LDRH from halfwords 0-3 in Strongly-ordered or Device memory.

Table 5.7. LDRH from Strongly-ordered or Device memory

Address[2:0]ARADDRARBURSTARSIZEARLEN
0x0 (halfword 0)0x00Incr16-bit1 data transfer
0x2 (halfword 1)0x02Incr16-bit1 data transfer
0x4 (halfword 2)0x04Incr16-bit1 data transfer
0x6 (halfword 3)0x06Incr16-bit1 data transfer

Note

A load of a halfword from Strongly-ordered or Device memory addresses 0x1, 0x3, 0x5, or 0x7 generates an alignment UsageFault.

LDR or LDM that transfers one register

Table 5.8 shows the values of ARADDR, ARBURST, ARSIZE, and ARLEN for a LDR or an LDM that transfers one register (an LDM1) in Strongly-ordered or Device memory.

Table 5.8. LDR or LDM1 from Strongly-ordered or Device memory

Address[2:0]ARADDRARBURSTARSIZEARLEN
0x0 (word 0)0x00Incr32-bit1 data transfer
0x4 (word 1)0x04Incr32-bit1 data transfer

Note

A load of a word from Strongly-ordered or Device memory addresses 0x1, 0x2, 0x3, 0x5, 0x6, or 0x7 generates an alignment UsageFault.

LDM that transfers two registers

Table 5.9 shows the values of ARADDR, ARBURST, ARSIZE, and ARLEN for a LDM that transfers two registers (an LDM2) in Strongly-ordered or Device memory.

Table 5.9. LDM2, Strongly-ordered or Device memory

Address[3:0]ARADDRARBURSTARSIZEARLEN
0x0 (word 0)0x00Incr32-bit1 data transfer
0x04Incr32-bit1 data transfer
0x4 (word 1)0x04Incr32-bit1 data transfer
0x08Incr32-bit1 data transfer
0x8 (word 2)0x08Incr32-bit1 data transfer
0x0CIncr32-bit1 data transfer
0xC (word 3)0x0CIncr32-bit1 data transfer
0x10Incr32-bit1 data transfer

Note

A load-multiple from address 0x1, 0x2, 0x3, 0x5, 0x6, 0x7, 0x9, 0xA, 0xB, 0xD, 0xE, or 0xF generates an alignment UsageFault.

STRB

Table 5.10 shows the values of AWADDR, AWBURST, AWSIZE, AWLEN, and WSTRB for an STRB to Strongly-ordered or Device memory over the AXIM interface.

Table 5.10. STRB to Strongly-ordered or Device memory

Address[2:0]AWADDRAWBURSTAWSIZEAWLENWSTRB
0x0 (byte 0)0x00Incr8-bit1 data transfer0b00000001
0x1 (byte 1)0x01Incr8-bit1 data transfer0b00000010
0x2 (byte 2)0x02Incr8-bit1 data transfer0b00000100
0x3 (byte 3)0x03Incr8-bit1 data transfer0b00001000
0x4 (byte 4)0x04Incr8-bit1 data transfer0b00010000
0x5 (byte 5)0x05Incr8-bit1 data transfer0b00100000
0x6 (byte 6)0x06Incr8-bit1 data transfer0b01000000
0x7 (byte 7)0x07Incr8-bit1 data transfer0b10000000

STRH

Table 5.11 shows the values of AWADDR, AWBURST, AWSIZE, AWLEN, and WSTRB for an STRH over the AXIM interface to Strongly-ordered or Device memory.

Table 5.11. STRH to Strongly-ordered or Device memory

Address[2:0]AWADDRAWBURSTAWSIZEAWLENWSTRB
0x0 (halfword 0)0x00Incr16-bit1 data transfer0b00000011
0x2 (halfword 1)0x02Incr16-bit1 data transfer0b00001100
0x4 (halfword 2)0x04Incr16-bit1 data transfer0b00110000
0x6 (halfword 3)0x06Incr16-bit1 data transfer0b11000000

Note

A store of a halfword to Strongly-ordered or Device memory addresses 0x1, 0x3, 0x5, or 0x7 generates an alignment UsageFault.

STR or STM of one register

Table 5.12 shows the values of AWADDR, AWBURST, AWSIZE, AWLEN, and WSTRB for an STR or an STM that transfers one register (an STM1) over the AXIM interface to Strongly-ordered or Device memory.

Table 5.12. STR or STM1 to Strongly-ordered or Device memory

Address[2:0]AWADDRAWBURSTAWSIZEAWLENWSTRB
0x0 (word 0)0x00Incr32-bit1 data transfer0b00001111
0x4 (word 1)0x04Incr32-bit1 data transfer0b11110000

Note

A store of a word to Strongly-ordered or Device memory addresses 0x1, 0x2, 0x3, 0x5, 0x6, or 0x7 generates an alignment UsageFault.

STM of five registers

Table 5.13 shows the values of AWADDR, AWBURST, AWSIZE, AWLEN, and first WSTRB for an STM that writes five registers (an STM5) over the AXIM interface to Strongly-ordered or Device memory.

Table 5.13. STM5 to Strongly-ordered or Device memory to word 0 or 1

Address[4:0]AWADDRAWBURSTAWSIZEAWLEN

First WSTRB

0x00 (word 0)0x00Incr32-bit2 data transfer0b00001111
0x08Incr32-bit2 data transfers0b00001111
0x10Incr32-bit1 data transfer0b00001111
0x04 (word 1)0x04Incr32-bit1 data transfer0b11110000
0x08Incr32-bit2 data transfers0b00001111
0x10Incr32-bit2 data transfers0b00001111

Note

A store-multiple to address 0x1, 0x2, 0x3, 0x5, 0x6, or 0x7 generates an alignment UsageFault.

Linefills

Loads and instruction fetches from Normal, cacheable memory that do not hit in the cache generate a cache linefill when the appropriate cache is enabled. Table 5.14 shows the values of ARADDR, ARBURST, ARSIZE, and ARLEN for cache linefills.

Table 5.14. Linefill behavior on the AXI interface

Address[4:0][a]ARADDRARBURSTARSIZEARLEN
0x00-0x070x00Wrap64-bit4 data transfers
0x08-0x0F0x08Wrap64-bit4 data transfers
0x10-0x170x10Wrap64-bit4 data transfers
0x18-0x1F0x18Wrap64-bit4 data transfers

[a] These are the bottom five bits of the address of the access that cause the linefill, that is, the address of the critical word.


Cache line write-back (eviction)

When a valid and dirty cache line is evicted from the data cache, a write-back of the data must occur. Table 5.15 shows the values of AWADDR, AWBURST, AWSIZE, and AWLEN for cache line write-backs, over the AXIM interface.

Table 5.15. Cache line write-back

AWADDR[4:0]AWBURSTAWSIZEAWLEN
0x00Incr64-bit4 data transfers

Non-cacheable reads

Load instructions accessing Non-cacheable Normal memory generate AXI bursts that are not necessarily the same size or length as the instruction implies. In addition, if the data to be read is contained in the store buffer, the instruction might not generate an AXI read transaction at all.

Non-cacheable, Write-Back no Write-Allocate or Write-Through writes

Store instructions to Non-cacheable, Write-Back no Write-Allocate Cacheable and Write-Through Cacheable memory generate AXI bursts that are not necessarily the same size or length as the instruction implies. The AXIM interface asserts byte-lane-strobes, WSTRB[7:0], to ensure that only the bytes that were written by the instruction are updated.

The tables in this section give examples of the types of AXI transaction that might result from various store instructions, accessing various addresses in Normal memory. They are provided as examples only, and are not an exhaustive description of the AXI transactions. Depending on the state of the processor, and the timing of the accesses, the actual bursts generated might have a different size and length to the examples shown, even for the same instruction.

In addition, write operations to Normal memory can be merged to create more complex AXI transactions. See Normal write merging for examples.

Table 5.16 shows possible values of AWADDR, AWBURST, AWSIZE, AWLEN, and WSTRB for an STRH to Normal memory.

Table 5.16. STRH to Cacheable write-through or Non-cacheable Normal memory

Address[2:0]AWADDRAWBURSTAWSIZEAWLEN

WSTRB

0x0 (byte 0)0x00Incr64-bit1 data transfer0b00000011
0x1 (byte 1)0x00Incr64-bit1 data transfer0b00000110
0x2 (byte 2)0x00Incr64-bit1 data transfer0b00001100
0x3 (byte 3)0x00Incr64-bit1 data transfer0b00011000
0x4 (byte 4)0x00Incr64-bit1 data transfer0b00110000
0x5 (byte 5)0x00Incr64-bit1 data transfer0b01100000
0x6 (byte 6)0x00Incr64-bit1 data transfer0b11000000
0x7 (byte 7)

0x00

Incr

64-bit

1 data transfer

0b10000000

0x08

Incr

64-bit

1 data transfer

0b00000001


Table 5.17 shows possible values of AWADDR, AWBURST, AWSIZE, AWLEN, and WSTRB for an STR that transfers one register to Normal memory through the AXIM interface.

Table 5.17. STR to Cacheable write-through or Non-cacheable Normal memory

Address[2:0]AWADDRAWBURSTAWSIZEAWLENWSTRB
0x0 (byte 0) (word 0)0x00Incr64-bit1 data transfer0b00001111
0x1 (byte 1)0x00Incr64-bit1 data transfer0b00011110
0x2 (byte 2)0x00Incr64-bit1 data transfer0b00111100
0x3 (byte 3)0x00Incr64-bit1 data transfer0b01111000
0x4 (byte 4) (word 1)0x00Incr64-bit1 data transfer0b11110000
0x5 (byte 5)

0x00

0x08

Incr

Incr

64-bit

64-bit

1 data transfer

1 data transfer

0b11100000

0b00000001

0x6 (byte 6)

0x00

0x08

Incr

Incr

64-bit

64-bit

1 data transfer

1 data transfer

0b11000000

0b00000011

0x7 (byte 5)

0x00

0x08

Incr

Incr

64-bit

64-bit

1 data transfer

1 data transfer

0b10000000

0b00000111


AXI transaction splitting

The processor splits AXI bursts when it accesses addresses across a cache line boundary, that is, a 32-byte boundary. An instruction that accesses memory across one or two 32-byte boundaries generates two or three AXI bursts respectively. The following examples show this behavior. They are provided as examples only, and are not an exhaustive description of the AXI transactions. Depending on the state of the processor, and the timing of the accesses, the actual bursts generated might have a different size and length to the examples shown, even for the same instruction.

For example, LDMIA R10, {R0-R5} loads six words from Non-cacheable, Normal memory. The number of AXI transactions generated by this instruction depends on the base address, R10:

  • If all six words are in the same cache line, there is a single AXI transaction. For example, for LDMIA R10, {R0-R5} with R10 = 0x1008, the interface might generate a burst of three, 64-bit read transfers, as shown in Table 5.18.

    Table 5.18. AXI transaction splitting, all six words in same cache line

    ARADDRARBURSTARSIZEARLEN
    0x1008Incr64-bit3 data transfers

  • If the data comes from two cache lines, then there are two AXI transactions. For example, for LDMIA R10, {R0-R5} with R10 = 0x1010, the interface might generate one burst of two 64-bit reads, and one burst of a single 64-bit read, as shown in Table 5.19.

    Table 5.19. AXI transaction splitting, data in two cache lines

    ARADDRARBURSTARSIZEARLEN
    0x1010Incr64-bit2 data transfers
    0x1020Incr64-bit1 data transfer

Table 5.20 shows possible values of ARADDR, ARBURST, ARSIZE, and ARLEN for an LDR to Non-cacheable Normal memory that crosses a cache line boundary.

Table 5.20. Non-cacheable LDR or LDM1 crossing a cache line boundary

Address[4:0]ARADDRARBURSTARSIZEARLEN
0x1D (byte 29)0x1DIncr32-bit1 data transfer
0x20Incr32-bit1 data transfer
0x1E (byte 30)0x1EIncr32-bit1 data transfer
0x20Incr32-bit1 data transfer
0x1F (byte 31)0x1FIncr32-bit1 data transfer
0x20Incr32-bit1 data transfer

Table 5.21 shows possible values of AWADDR, AWBURST, AWSIZE, AWLEN, and WSTRB for an STRH to Non-cacheable Normal memory that crosses a cache line boundary.

Table 5.21. Non-cacheable STRH crossing a cache line boundary

Address[4:0]AWADDRAWBURSTAWSIZEAWLENWSTRB
0x1F (byte 31)0x18Incr64-bit1 data transfer0b10000000
0x20Incr64-bit1 data transfer0b00000001

Normal write merging

A store instruction to Non-cacheable, Write-Back no Write-Allocate Cacheable, or Write-Through Cacheable Normal memory might not result in an AXI transfer because of the merging of store data in the internal buffers.

The store buffer can detect when it contains more than one write request to the same cache line for Write-Through Cacheable or Non-cacheable Normal memory. This means it can combine the data from more than one instruction into a single write burst to improve the efficiency of the AXI interface. If the AXIM receives several write requests that do not form a single contiguous burst it can choose to output a single burst, with the WSTRB signal low for the bytes that do not have any data.

For write accesses to Normal memory, the store can perform writes out of order, if there are no address dependencies. It can do this to best use its ability to merge accesses.

The instruction sequence in Example 5.1 shows the merging of writes.

Example 5.1. Write merging

MOV r0, #0x4000
STRH  r1, [r0, #0x18]; Store a halfword at 0x4018
STR   r2, [r0, #0xC] ; Store a word at 0x400C
STMIA r0, {r4-r7}    ; Store four words at 0x4000
STRB  r3, [r0, #0x1D]; Store a byte at 0x401D

Table 5.22 shows the values of AWADDR, AWBURST, AWSIZE, AWLEN, and WSTRB generated if the memory at address 0x4000 is marked as Strongly-ordered or Device type memory.

Table 5.22. AXI transactions for Strongly-ordered or Device type memory

AWADDRAWBURSTAWSIZEAWLENWSTRB
0x4018Incr16-bit1 data transfer0b00000011
0x400CIncr32-bit1 data transfer0b11110000
0x4000

Incr

32-bit2 data transfers

0b00001111

0b11110000

0x4008

Incr

32-bit2 data transfers

0b00001111

0b11110000

0x401DIncr8-bit1 data transfer0b00100000

In Example 5.1, each store instruction produces an AXI burst of the same size as the data written by the instruction.

Table 5.23 shows a possible resulting transaction if the same memory is marked as Non-cacheable Normal, or Write-Through Cacheable.

Table 5.23. AXI transactions for Non-cacheable Normal or Write-Through Cacheable memory

AWADDRAWBURSTAWSIZEAWLENWSTRB
0x4000Incr64-bit4 data transfers

0b11111111

0b11111111

0b00000000

0b00100011


In this example:

  • The store buffer has merged the STRB and STRH writes into one buffer entry, and therefore a single AXI transfer, the fourth in the burst.

  • The writes, that occupy three buffer entries, have been merged into a single AXI burst of four transfers.

  • The write generated by the STR instruction has not occurred, because it was overwritten by the STM instruction.

  • The write transfers have occurred out of order with respect to the original program order.

The transactions shown in Table 5.23 show this behavior. They are provided as examples only, and are not an exhaustive description of the AXI transactions. Depending on the state of the processor, and the timing of the accesses, the actual bursts generated might have a different size and length to the examples shown, even for the same instruction.

If the same memory is marked as Write-Back Cacheable, and the addresses are allocated into a cache line, no AXI write transactions occur until the cache line is evicted and performs a write-back transaction. See Cache line write-back (eviction).

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