5.8.4. TCM interface protocol

Each TCM interface operates independently of each other, and each might perform either a read or a write access in a particular clock cycle. In addition to the address and data signals, the TCM interfaces also provide information about the source of an access and whether it is privileged or not. Therefore, it is possible to determine whether an access results from an instruction fetch from the PFU, a data access from the LSU, an SQ access, an MBIST interface access, or a DMA transfer from the AHBS interface.

During read accesses, an external TCM memory controller can indicate that the processor must wait one or more clock cycles before capturing the read data from the interface. The controller can also indicate that an error occurred during a read or a write access and that the processor must take a bus fault. The controller might, for example, use this error to indicate a privilege violation by decoding the address, privilege indication, or access source information. For more information about TCM errors, see Faults.

If the TCM memory controller supports ECC error detection and correction it can indicate to the processor that an access must be retried to return the corrected data. The TCM retry functionality in the processor must be enabled to support external TCM error correction by setting the ITCMCR.RETEN or DTCMCR.RETEN bits to 1. See Instruction and Data Tightly-Coupled Memory Control Registers.

Note

In a design where the TCM retry functionality is enabled and the TCM memory controller signals a retry in the retry phase of a debugger read request:

  • The TCM access is not retried.

  • An ERROR response is signaled to the debugger on the AHBD interface.

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