5.9. L1 caches

This section describes the behavior of the optional L1 caches in the Cortex-M7 processor memory system.

The memory system is configured during implementation and can include instruction and data caches of varying sizes. You can configure whether each cache controller is included and, if it is, configure the size of each cache independently. The cached instructions or data are fetched from external memory using the AXIM interface. The cache controllers use RAMs that are integrated into the Cortex-M7 processor during implementation.

Any access that is not for a TCM or the AHBP interface is handled by the appropriate cache controller. If the access is to Non-shared cacheable memory, and the cache is enabled, a lookup is performed in the cache and, if found in the cache, that is, a cache hit, the data is fetched from or written into the cache. When the cache is not enabled and for Non-cacheable or Shared memory the accesses are performed using the AXIM interface.

Both caches allocate a memory location to a cache line on a cache miss because of a read, that is, all cacheable locations are Read-Allocate. In addition, the data cache can allocate on a write access if the memory location is marked as Write-Allocate. When a cache line is allocated, the appropriate memory is fetched into a linefill buffer by the AXIM interface before being written to the cache. The linefill buffers always fetch the requested data first, return it, and fetch the rest of the cache line. This enables the data read without waiting for the linefill to complete and is known as critical word first and non-blocking behavior. If subsequent instructions require data from the same cache line, this can also be returned when it has been fetched without waiting for the linefill to complete, that is, the caches also support streaming. If an error is reported to the AXIM interface for a linefill, the linefill does not update the cache RAMs.

A synchronous fault is generated if the faulting data is used by a non-speculative read in the processor. An asynchronous fault is generated by a line-fill when an external fault occurs if write data from an address configured as Write-Back has been merged into the line from the store buffer. See Store buffer.

The data cache is four-way set-associative, the instruction cache is two-way set-associative. Both caches use a line-length of 32-bytes. If all the cache lines in a set are valid, to allocate a different address to the cache, the cache controller must evict a line from the cache.

Writes accesses that hit in the data cache are written into the cache RAMs. If the memory location is marked as Write-Through, the write is also performed on the AXIM interface, so that the data stored in the RAM remains coherent with the external memory system. If the memory is Write-Back, the cache line is marked as dirty, and the write is only performed on the AXIM interface when the line is evicted. When a dirty cache line is evicted, the data is passed to the write buffer in the AXIM interface to be written to the external memory system.

The cache controllers also manage the cache maintenance operations described in Cache maintenance operations.

Each cache can also be configured with ECC. If ECC is implemented and enabled, then the tags associated with each line, and data read from the cache are checked whenever a lookup is performed in the cache and, if possible, the data is corrected before being used in the processor. A full description of ECC error checking and correction is beyond the scope of this document. Contact Arm if you require more information.

For more information on the general rules about memory attributes and behavior, see the Arm®v7-M Architecture Reference Manual.

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