8.1. About the FPU

The Cortex-M7 processor with FPU is an implementation of the single-precision and double-precision variant of the ARMv7-M Architecture with Floating-Point Extension (FPv5).

The FPv5 extensions features are:

Table 8.1 shows the ISA supported for the different configurations of the Cortex-M7 processor.

Table 8.1. Cortex-M7 ISA Support

ConfigurationISA supported
Processor with no floating-pointv7E-M
Processor with single-precision floating-pointv7E-M + FPv5-SP-D16-M
Processor with single-precision and double-precision floating-pointv7E-M + FPv5-DP-D16-M

It provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard.

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