8.3. FPU programmers model

Table 8.2 shows the floating-point system registers in the Cortex-M7 processor with FPU, when implemented. These registers are described in the Arm®v7-M Architecture Reference Manual.

Table 8.2.  Floating-point system registers

AddressNameTypeResetDescription
0xE000EF34FPCCRRW0xC0000000Context Control Register
0xE000EF38FPCARRW-Context Address Register
0xE000EF3CFPDSCRRW0x00000000Default Status Control Register
0xE000EF40MVFR0RO0x10110021[a]Media and VFP Feature Register 0
0x10110221[b]
0xE000EF44MVFR1RO0x11000011[a]Media and VFP Feature Register 1
0x12000011[b]
0xE000EF48MVFR2RO0x00000040Media and VFP Feature Register 2

[a] Single-precision only FPU.

[b] Single-precision and double-precision FPU.


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