5.9.4. Cache interaction with memory system

After you enable or disable the instruction cache, you must issue an ISB instruction to flush the pipeline. This ensures that all subsequent instruction fetches see the effect of enabling or disabling the instruction cache.

After reset, you must invalidate each cache before enabling it.

When disabling the data cache, you must clean the entire cache to ensure that any dirty data is flushed to external memory.

Before enabling the data cache, you must invalidate the entire data cache because external memory might have changed from when the cache was disabled.

Before enabling the instruction cache, you must invalidate the entire instruction cache if external memory might have changed since the cache was disabled.

See Chapter 4 Initialization for example code suitable for initializing and enabling the instruction and data caches.

Copyright © 2014-2016, 2018 Arm. All rights reserved.ARM DDI 0489F
Non-ConfidentialID121118