7.3. NVIC programmers model

This section describes the NVIC registers whose implementation is specific to this processor. Other registers are described in the Arm®v7-M Architecture Reference Manual. Table 7.1 shows the NVIC registers.

Table 7.1. NVIC registers

AddressNameType

Reset

Description
0xE000E004ICTRRO-Interrupt Controller Type Register
0xE000E100-0xE000E11CNVIC_ISER0-NVIC_ISER7RW0x00000000Interrupt Set-Enable Registers
0xE000E180-0xE000E19CNVIC_ICER0-NVIC_ICER7RW0x00000000Interrupt Clear-Enable Registers
0xE000E200-0xE000E21CNVIC_ISPR0-NVIC_ISPR7RW0x00000000Interrupt Set-Pending Registers
0xE000E280-0xE000E29CNVIC_ICPR0-NVIC_ICPR7RW0x00000000Interrupt Clear-Pending Registers
0xE000E300-0xE000E31CNVIC_IABR0-NVIC_IABR7RO0x00000000Interrupt Active Bit Register
0xE000E400-0xE000E4ECNVIC_IPR0-NVIC_IPR59RW0x00000000Interrupt Priority Register

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