5.1. About the memory system

This section provides an overview of the Cortex-M7 processor memory system.

The Cortex-M7 processor memory system can be configured during implementation and integration. It consists of:

The cache architecture is Harvard, that is, only instructions can be fetched from the instruction cache, and only data can be read from and written to the data cache.

In parallel with each of the caches are two areas of dedicated RAM accessible to both the instruction and data sides. These are regions of TCM.

Instruction TCM (ITCM) uses the ITCM interface and the Data TCM (DTCM) uses two interfaces, D0TCM and D1TCM. Figure 1.3 shows this.

The ITCM interface is 64-bits wide. The DTCM is divided into two 32-bit wide interfaces, D0TCM and D1TCM. The upper 32-bits of data is on the D1TCM interface and the lower 32-bits of the data is on the D0TCM interface.

Memory accesses to the ITCM, required for fetching instructions and for data transfer instructions, are performed if the address is in an enabled TCM region. Remaining instruction accesses and remaining data accesses that are not in a peripheral interface region are looked up in the appropriate L1 cache if they are cacheable. Accesses that are not serviced by the memory system are passed through the AXI master (AXIM) interface or the AHBP interface to the external memory system connected to the processor.

The Cortex-M7 processor only respects the memory ordering restrictions described in the Arm®v7-M Architecture Reference Manual in case of memory transfers initiated by the same master interface. Ordering between different interfaces is not guaranteed without the use of barrier instructions.

Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors. Each TCM interface can support external logic to the processor to report to the processor that an error has occurred.

The processor includes support for direct access to the TCM through the AHBS interface. The interface provides high bandwidth for DMA traffic to the memory and can be used when the remainder of the processor is in low-power standby mode, with the internal clock disabled.

The optional MPU handles both the instruction and data memory accesses. The MPU is responsible for protection checking, address access permissions, and memory attributes for all accesses. Some of these attributes can be passed through the AXIM interface or AHBP interface to the external memory system.

The memory system includes a monitor for exclusive accesses. Exclusive load and store instructions, for example LDREX and STREX, can be used with the appropriate memory monitoring to provide inter-process or inter-processor synchronization and semaphores. See the Arm®v7-M Architecture Reference Manual for more information.

The processor is designed for use in chip designs that use the AMBA 4 AXI and AMBA 3 AHB-Lite protocols.

Copyright © 2014-2016, 2018 Arm. All rights reserved.ARM DDI 0489F
Non-ConfidentialID121118