2.4.2. Unaligned accesses that cross regions

The Cortex-M7 processor supports ARMv7 unaligned accesses, and performs all accesses as single, unaligned accesses. They are converted into two or more aligned accesses internally and are performed on the external interfaces of the processor.

Note

All Cortex-M7 processor external accesses are aligned.

Unaligned support is only available for load/store singles (LDR, LDRH, STR, STRH). Load/store double already supports word aligned accesses, but does not permit other unaligned accesses, and generates a fault if this is attempted.

Unaligned accesses that cross memory map boundaries are architecturally unpredictable. The processor behavior is boundary dependent. Unaligned accesses are not supported to PPB space, and so there are no boundary crossing cases for PPB accesses.

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