5.5.3. AXI privilege information

AXI provides information about the privilege level of an access on the ARPROT and AWPROT signals. However, when accesses might be cached or merged together, the resulting transaction can have both privileged and user data combined. If this happens, the Cortex-M7 processor marks the transaction as privileged, even if it was initiated by a user process.

Table 5.5 shows Cortex-M7 mode and APROT values.

Table 5.5. Cortex-M7 mode and APROT values

Processor modeType of accessValue of APROT
-Cacheable read accessAlways marked as Privileged
User Non-cacheable read accessUser except for LDM, LDRD and POP when the L1 data cache is implemented
PrivilegedPrivileged
User Device or Strongly-ordered read accessUser
PrivilegedPrivileged
-Cacheable write accessAlways marked as Privileged
User Device or Strongly-ordered write accessUser
PrivilegedPrivileged
User Normal non-cacheable write accessPrivileged, except for STREXB, STREXH, and STREX
PrivilegedPrivileged

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