ARM® CoreSight™ ETM-M7 Technical Reference Manual

Revision: r0p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the CoreSight ETM-M7
1.1.1. The CoreSight debug environment
1.2. Compliance
1.2.1. Trace macrocell
1.2.2. Interconnect architecture
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.6. Test features
1.7. Product documentation and design flow
1.7.1. Documentation
1.7.2. Design flow
1.8. Product revisions
2. Functional Description
2.1. About the functions
2.1.1. Processor interface
2.1.2. Instruction trace generator
2.1.3. Data trace generator
2.1.4. FIFO
2.1.5. Resources and filtering logic
2.1.6. ATB interfaces
2.1.7. APB interface
2.1.8. Global timestamping
2.2. Interfaces
2.2.1. ETMEVENT connectivity
2.3. Clocking and resets
2.3.1. ETM-M7 clock
2.3.2. ETM-M7 low power control
2.3.3. ETM-M7 reset
2.3.4. Access permissions and power domains
2.4. Operation
2.4.1. Implementation defined registers
2.4.2. Precise TraceEnable events
2.4.3. Parallel instruction execution
2.4.4. Trace and comparator features
2.4.5. Packet formats
2.4.6. Resource selection
2.4.7. Trace flush behavior
2.4.8. Low power state behavior
2.4.9. Cycle counter
2.4.10. Micro-architectural exceptions
2.4.11. Trace synchronization
2.4.12. Event tracing and triggers
3. Programmers Model
3.1. About the programmers model
3.2. Modes of operation and execution
3.2.1. Controlling ETM programming
3.2.2. Programming and reading ETM registers
3.3. Register summary
3.3.1. Functional grouping of registers
3.4. Register descriptions
3.4.1. Programming Control Register
3.4.2. Processor Select Control Register
3.4.3. Status Register
3.4.4. Trace Configuration Register
3.4.5. Event Control 0 Register
3.4.6. Event Control 1 Register
3.4.7. Stall Control Register
3.4.8. Global Timestamp Control Register
3.4.9. Synchronization Period Register
3.4.10. Cycle Count Control Register
3.4.11. Branch Broadcast Control Register
3.4.12. Trace ID Register
3.4.13. ViewInst Main Control Register
3.4.14. ViewInst Include/Exclude Control Register
3.4.15. ViewInst Start-Stop Processor Comparator Control Register
3.4.16. ViewInst Start/Stop Control Register
3.4.17. ViewData Main Control Register
3.4.18. ViewData Include/Exclude Single Address Comparator Register
3.4.19. ViewData Include/Exclude Address Range Comparator Register
3.4.20. Sequencer State Transition Control Registers 0-2
3.4.21. Sequencer Reset Control Register
3.4.22. Sequencer State Register
3.4.23. Counter Reload Value Registers 0-1
3.4.24. Counter Control Registers 0-1
3.4.25. Counter Value Registers 0-1
3.4.26. ID Register 8-13
3.4.27. Implementation Specific Register 0
3.4.28. ID Register 0
3.4.29. ID Register 1
3.4.30. ID Register 2
3.4.31. ID Register 3
3.4.32. ID Register 4
3.4.33. ID Register 5
3.4.34. Resource Selection Registers 2-15
3.4.35. Single-shot Comparator Control Register 0
3.4.36. Single-shot Comparator Status Register 0
3.4.37. Single-shot Processor Comparator Input Control Register
3.4.38. OS Lock Status Register
3.4.39. Power Down Control Register
3.4.40. Power Down Status Register
3.4.41. Address Comparator Value Registers 0-7
3.4.42. Address Comparator Access Type Registers 0-7
3.4.43. Data Value Comparator Value Registers 0-1
3.4.44. Data Value Comparator Mask Registers 0-1
3.4.45. Integration test registers
3.4.46. Claim Tag Set Register
3.4.47. Claim Tag Clear Register
3.4.48. Software Lock Access Register
3.4.49. Software Lock Status Register
3.4.50. Authentication Status Register
3.4.51. Device Architecture Register
3.4.52. Device ID Register
3.4.53. Device Type Register
3.4.54. Peripheral Identification Registers
3.4.55. Component Identification Registers
A. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. ETM-M7 system diagram
2.1. ETM-M7 block diagram
2.2. Trigger event resource selection
3.1. Programming ETM-M7 registers
3.2. TRCPRGCTLR bit assignments
3.3. TRCPROCSELR bit assignments
3.4. TRCSTATR bit assignments
3.5. TRCCONFIGR bit assignments
3.6. TRCEVENTCTL0R bit assignments
3.7. TRCEVENTCTL1R bit assignments
3.8. TRCSTALLCTLR bit assignments
3.9. TRCTSCTLR bit assignments
3.10. TRCSYNCPR bit assignments
3.11. TRCCCCTLR bit assignments
3.12. TRCBBCTLR bit assignments
3.13. TRCTRACEIDR bit assignments
3.14. TRCVICTLR bit assignments
3.15. TRCVIIECTLR bit assignments
3.16. TRCVIPCSSCTLR bit assignments
3.17. TRCVISSCTLR bit assignments
3.18. TRCVDCTLR bit assignments
3.19. TRCVDSACCTLR bit assignments
3.20. TRCVDARCCTLR bit assignments
3.21. TRCSEQEVRn bit assignments
3.22. TRCSEQRSTEVR bit assignments
3.23. TRCSEQSTR bit assignments
3.24. TRCCNTRLDVRn bit assignments
3.25. TRCCNTCTLRn bit assignments
3.26. TRCCNTVRn bit assignments
3.27. TRCIDR8 bit assignments
3.28. TRCIDR9 bit assignments
3.29. TRCIDR10 bit assignments
3.30. TRCIDR11 bit assignments
3.31. TRCIDR12 bit assignments
3.32. TRCIDR13 bit assignments
3.33. TRCIMSPEC0 bit assignments
3.34. TRCIDR0 bit assignments
3.35. TRCIDR1 bit assignments
3.36. TRCIDR2 bit assignments
3.37. TRCIDR3 bit assignments
3.38. TRCIDR4 bit assignments
3.39. TRCIDR5 bit assignments
3.40. TRCRSCTLRn bit assignments
3.41. TRCSSCCR0 bit assignments
3.42. TRCSSCSR0 bit assignments
3.43. TRCSSPCICR0 bit assignments
3.44. TRCOSLSR bit assignments
3.45. TRCPDCR bit assignments
3.46. TRCPDSR bit assignments
3.47. TRCACVRn bit assignments
3.48. TRCACATR0 bit assignments
3.49. TRCACATR1 bit assignments
3.50. TRCDVCVRn bit assignments
3.51. TRCDVCMRn bit assignments
3.52. TRCITMISCOUTR bit assignments
3.53. TRCITMISCINR bit assignments
3.54. TRCITATBIDR bit assignments
3.55. TRCITDDATAR bit assignments
3.56. TRCITIDATAR bit assignments
3.57. TRCITDATBINR bit assignments
3.58. TRCITIATBINR bit assignments
3.59. TRCITDATBOUTR bit assignments
3.60. TRCITIATBOUTR bit assignments
3.61. TRCITCTRL bit assignments
3.62. TRCCLAIMSET bit assignments
3.63. TRCCLAIMCLR bit assignments
3.64. TRCLAR bit assignments
3.65. TRCLSR bit assignments
3.66. TRCAUTHSTATUS bit assignments
3.67. TRCDEVARCH bit assignments
3.68. TRCDEVID bit assignments
3.69. TRCDEVTYPE bit assignments
3.70. Mapping between TRCPIDR0-7 and the Peripheral ID value
3.71. Peripheral ID fields
3.72. Mapping between TRCCIDR0-3 and the Component ID value

List of Tables

1. Typographical conventions
1.1. ETM-M7 features with implementation-defined number of instances or size
1.2. ETM-M7 implementation of optional features
2.1. ETMEVENTS connections
2.2. ETMEVENTM connections to CTI
2.3. Instruction-only resource selection
2.4. Instruction and data resource selection
3.1. ETM-M7 register summary
3.2. General control and ID registers
3.3. Trace filtering control registers
3.4. Derived resource registers
3.5. Implementation specific and identification registers
3.6. Resource selection registers
3.7. Single-shot comparator registers
3.8. Power control registers
3.9. Comparator registers
3.10. Integration test registers
3.11. CoreSight management registers
3.12. TRCPRGCTLR bit assignments
3.13. TRCPROCSELR bit assignments
3.14. TRCSTATR bit assignments
3.15. TRCCONFIGR bit assignments for instruction and data configuration
3.16. TRCCONFIGR bit assignments for instruction trace only configuration
3.17. TRCEVENTCTL0R bit assignments
3.18. TRCEVENTCTL1R bit assignments
3.19. TRCSTALLCTLR bit assignments
3.20. TRCTSCTLR bit assignments
3.21. TRCSYNCPR bit assignments
3.22. TRCCCCTLR bit assignments
3.23. TRCBBCTLR bit assignments
3.24. TRCTRACEIDR bit assignments
3.25. TRCVICTLR bit assignments
3.26. TRCVIIECTLR bit assignments
3.27. TRCVIPCSSCTLR bit assignments
3.28. TRCVISSCTLR bit assignments
3.29. TRCVDCTLR bit assignments
3.30. TRCVDSACCTLR bit assignments
3.31. TRCVDARCCTLR bit assignments
3.32. TRCSEQEVRn bit assignments
3.33. TRCSEQRSTEVR bit assignments
3.34. TRCSEQSTR bit assignments
3.35. TRCCNTRLDVRn bit assignments
3.36. TRCCNTCTLRn bit assignments
3.37. TRCCNTVRn bit assignments
3.38. TRCIDR8 bit assignments
3.39. TRCIDR9 bit assignments
3.40. TRCIDR10 bit assignments
3.41. TRCIDR11 bit assignments
3.42. TRCIDR12 bit assignments
3.43. TRCIDR13 bit assignments
3.44. TRCIMSPEC0 bit assignments
3.45. TRCIDR0 bit assignments
3.46. TRCIDR1 bit assignments
3.47. TRCIDR2 bit assignments
3.48. TRCIDR3 bit assignments
3.49. TRCIDR4 bit assignments
3.50. TRCIDR5 bit assignments
3.51. TRCRSCTLRn bit assignments
3.52. TRCSSCCR0 bit assignments
3.53. TRCSSCSR0 bit assignments
3.54. TRCSSPCICR0 bit assignments
3.55. TRCOSLSR bit assignments
3.56. TRCPDCR bit assignments
3.57. TRCPDSR bit assignments
3.58. TRCACVRn bit assignments
3.59. TRCACATR0 bit assignments
3.60. TRCACATR1 bit assignments
3.61. TRCDVCVRn bit assignments
3.62. TRCDVCMRn bit assignments
3.63. Output signals that the integration test registers can control
3.64. Input signals that the integration test registers can read
3.65. TRCITMISCOUTR bit assignments
3.66. TRCITMISCINR bit assignments
3.67. TRCITATBIDR bit assignments
3.68. TRCITDDATAR bit assignments
3.69. TRCITIDATAR bit assignments
3.70. TRCITDATBINR bit assignments
3.71. TRCITIATBINR bit assignments
3.72. TRCITDATBOUTR bit assignments
3.73. TRCITIATBOUTR bit assignments
3.74. TRCITCTRL bit assignments
3.75. TRCCLAIMSET bit assignments
3.76. TRCCLAIMCLR bit assignments
3.77. TRCLAR bit assignments
3.78. TRCLSR bit assignments
3.79. TRCAUTHSTATUS bit assignments
3.80. TRCDEVARCH bit assignments
3.81. TRCDEVID bit assignments
3.82. TRCDEVTYPE bit assignments
3.83. TCRPIDR0-7 bit assignments
3.84. TRCCIDR0-3 bit assignments
A.1. Issue A
A.2. Differences between issue A and issue B
A.3. Differences between issue B and issue C
A.4. Differences between issue C and issue D

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Revision History
Revision A25 April 2014First release for r0p0
Revision B05 December 2014First release for r0p1
Revision C19 March 2015Second release for r0p1
Revision D06 July 2015Third release for r0p1
Copyright © 2014, 2015 ARM. All rights reserved.ARM DDI 0494D
Non-ConfidentialID082615