ARM® Cortex®-A53 MPCore Processor Technical Reference Manual

Revision: r0p2


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the Cortex-A53 processor
1.2. Compliance
1.2.1. ARM architecture
1.2.2. Interconnect architecture
1.2.3. Generic Interrupt Controller architecture
1.2.4. Generic Timer architecture
1.2.5. Debug architecture
1.2.6. Embedded Trace Macrocell architecture
1.3. Features
1.4. Interfaces
1.5. Implementation options
1.5.1. Processor configuration
1.6. Test features
1.7. Product documentation and design flow
1.7.1. Documentation
1.7.2. Design flow
1.8. Product revisions
2. Functional Description
2.1. About the Cortex-A53 processor functions
2.1.1. Instruction Fetch Unit
2.1.2. Data Processing Unit
2.1.3. Advanced SIMD and Floating-point Extension
2.1.4. Cryptography Extension
2.1.5. Translation Lookaside Buffer
2.1.6. Data side memory system
2.1.7. L2 memory system
2.1.8. Cache protection
2.1.9. Debug and trace
2.2. Interfaces
2.2.1. Master memory interface
2.2.2. Accelerator Coherency Port
2.2.3. External debug interface
2.2.4. Trace interface
2.2.5. CTI
2.2.6. DFT
2.2.7. MBIST
2.2.8. Q-channel
2.3. Clocking and resets
2.3.1. Clocks
2.3.2. Input synchronization
2.3.3. Resets
2.4. Power management
2.4.1. Power domains
2.4.2. Power modes
2.4.3. Event communication using WFE or SEV
2.4.4. Communication to the Power Management Controller
3. Programmers Model
3.1. About the programmers model
3.1.1. Advanced SIMD and Floating-point support
3.1.2. Memory model
3.1.3. Jazelle implementation
3.1.4. Modes of operation
3.2. ARMv8-A architecture concepts
3.2.1. Execution state
3.2.2. Exception levels
3.2.3. Security state
3.2.4. Rules for changing execution state
3.2.5. Stack pointer selection
3.2.6. ARMv8 security model
3.2.7. Instruction set state
3.2.8. AArch32 execution modes
4. System Control
4.1. About system control
4.1.1. AArch32 registers affected by CP15SDISABLE
4.2. AArch64 register summary
4.2.1. AArch64 identification registers
4.2.2. AArch64 exception handling registers
4.2.3. AArch64 virtual memory control registers
4.2.4. AArch64 other system control registers
4.2.5. AArch64 performance monitor registers
4.2.6. AArch64 reset registers
4.2.7. AArch64 secure registers
4.2.8. AArch64 virtualization registers
4.2.9. AArch64 GIC system registers
4.2.10. AArch64 Generic Timer registers
4.2.11. AArch64 thread registers
4.2.12. AArch64 implementation defined registers
4.2.13. AArch64 address registers
4.3. AArch64 register descriptions
4.3.1. Main ID Register, EL1
4.3.2. Multiprocessor Affinity Register
4.3.3. Revision ID Register
4.3.4. AArch32 Processor Feature Register 0
4.3.5. AArch32 Processor Feature Register 1
4.3.6. AArch32 Debug Feature Register 0
4.3.7. AArch32 Auxiliary Feature Register 0
4.3.8. AArch32 Memory Model Feature Register 0
4.3.9. AArch32 Memory Model Feature Register 1
4.3.10. AArch32 Memory Model Feature Register 2
4.3.11. AArch32 Memory Model Feature Register 3
4.3.12. AArch32 Instruction Set Attribute Register 0
4.3.13. AArch32 Instruction Set Attribute Register 1
4.3.14. AArch32 Instruction Set Attribute Register 2
4.3.15. AArch32 Instruction Set Attribute Register 3
4.3.16. AArch32 Instruction Set Attribute Register 4
4.3.17. AArch32 Instruction Set Attribute Register 5
4.3.18. AArch64 Processor Feature Register 0
4.3.19. AArch64 Debug Feature Register 0, EL1
4.3.20. AArch64 Instruction Set Attribute Register 0, EL1
4.3.21. AArch64 Memory Model Feature Register 0, EL1
4.3.22. Cache Size ID Register
4.3.23. Cache Level ID Register
4.3.24. Auxiliary ID Register
4.3.25. Cache Size Selection Register
4.3.26. Cache Type Register
4.3.27. Data Cache Zero ID Register
4.3.28. Virtualization Processor ID Register
4.3.29. Virtualization Multiprocessor ID Register
4.3.30. System Control Register, EL1
4.3.31. Auxiliary Control Register, EL1
4.3.32. Auxiliary Control Register, EL2
4.3.33. Auxiliary Control Register, EL3
4.3.34. Architectural Feature Access Control Register
4.3.35. System Control Register, EL2
4.3.36. Hypervisor Configuration Register
4.3.37. Hyp Debug Control Register
4.3.38. Architectural Feature Trap Register, EL2
4.3.39. Hyp System Trap Register
4.3.40. Hyp Auxiliary Configuration Register
4.3.41. System Control Register, EL3
4.3.42. Secure Configuration Register
4.3.43. Secure Debug Enable Register
4.3.44. Translation Table Base Register 0, EL1
4.3.45. Translation Table Base Register 1
4.3.46. Architectural Feature Trap Register, EL3
4.3.47. Monitor Debug Configuration Register, EL3
4.3.48. Translation Control Register, EL1
4.3.49. Translation Control Register, EL2
4.3.50. Virtualization Translation Control Register, EL2
4.3.51. Domain Access Control Register
4.3.52. Translation Table Base Register 0, EL3
4.3.53. Translation Control Register, EL3
4.3.54. Auxiliary Memory Attribute Indirection Register, EL1, EL2 and EL3
4.3.55. Auxiliary Fault Status Register 0, EL1, EL2 and EL3
4.3.56. Auxiliary Fault Status Register 1, EL1, EL2 and EL3
4.3.57. Exception Syndrome Register, EL1
4.3.58. Instruction Fault Status Register, EL2
4.3.59. Exception Syndrome Register, EL2
4.3.60. Exception Syndrome Register, EL3
4.3.61. Fault Address Register, EL1
4.3.62. Fault Address Register, EL2
4.3.63. Hypervisor IPA Fault Address Register, EL2
4.3.64. L2 Control Register
4.3.65. L2 Extended Control Register
4.3.66. L2 Auxiliary Control Register
4.3.67. Fault Address Register, EL3
4.3.68. Physical Address Register, EL1
4.3.69. Memory Attribute Indirection Register, EL1
4.3.70. Memory Attribute Indirection Register, EL2
4.3.71. Memory Attribute Indirection Register, EL3
4.3.72. Vector Base Address Register, EL1
4.3.73. Vector Base Address Register, EL2
4.3.74. Vector Base Address Register, EL3
4.3.75. Reset Vector Base Address Register, EL3
4.3.76. Reset Management Register
4.3.77. Interrupt Status Register
4.3.78. CPU Auxiliary Control Register, EL1
4.3.79. CPU Extended Control Register, EL1
4.3.80. CPU Memory Error Syndrome Register
4.3.81. L2 Memory Error Syndrome Register
4.3.82. Configuration Base Address Register, EL1
4.4. AArch32 register summary
4.4.1. c0 registers
4.4.2. c1 registers
4.4.3. c2 registers
4.4.4. c3 registers
4.4.5. c4 registers
4.4.6. c5 registers
4.4.7. c6 registers
4.4.8. c7 registers
4.4.9. c9 registers
4.4.10. c10 registers
4.4.11. c11 registers
4.4.12. c12 registers
4.4.13. c13 registers
4.4.14. c14 registers
4.4.15. c15 registers
4.4.16. 64-bit registers
4.4.17. AArch32 Identification registers
4.4.18. AArch32 Virtual memory control registers
4.4.19. AArch32 Fault handling registers
4.4.20. AArch32 Other System control registers
4.4.21. AArch32 Address registers
4.4.22. AArch32 Thread registers
4.4.23. AArch32 Performance monitor registers
4.4.24. AArch32 Secure registers
4.4.25. AArch32 Virtualization registers
4.4.26. AArch32 GIC system registers
4.4.27. AArch32 Generic Timer registers
4.4.28. AArch32 Implementation defined registers
4.5. AArch32 register descriptions
4.5.1. Main ID Register
4.5.2. Multiprocessor Affinity Register
4.5.3. Revision ID Register
4.5.4. TCM Type Register
4.5.5. TLB Type Register
4.5.6. Processor Feature Register 0
4.5.7. Processor Feature Register 1
4.5.8. Debug Feature Register 0
4.5.9. Auxiliary Feature Register 0
4.5.10. Memory Model Feature Register 0
4.5.11. Memory Model Feature Register 1
4.5.12. Memory Model Feature Register 2
4.5.13. Memory Model Feature Register 3
4.5.14. Instruction Set Attribute Register 0
4.5.15. Instruction Set Attribute Register 1
4.5.16. Instruction Set Attribute Register 2
4.5.17. Instruction Set Attribute Register 3
4.5.18. Instruction Set Attribute Register 4
4.5.19. Instruction Set Attribute Register 5
4.5.20. Cache Size ID Register
4.5.21. Cache Level ID Register
4.5.22. Auxiliary ID Register
4.5.23. Cache Size Selection Register
4.5.24. Cache Type Register
4.5.25. Virtualization Processor ID Register
4.5.26. Virtualization Multiprocessor ID Register
4.5.27. System Control Register
4.5.28. Auxiliary Control Register
4.5.29. Architectural Feature Access Control Register
4.5.30. Secure Configuration Register
4.5.31. Secure Debug Enable Register
4.5.32. Non-Secure Access Control Register
4.5.33. Secure Debug Control Register
4.5.34. Hyp Auxiliary Control Register
4.5.35. Hyp System Control Register
4.5.36. Hyp Configuration Register
4.5.37. Hyp Configuration Register 2
4.5.38. Hyp Debug Control Register
4.5.39. Hyp Architectural Feature Trap Register
4.5.40. Translation Table Base Register 0
4.5.41. Translation Table Base Register 1
4.5.42. Translation Table Base Control Register
4.5.43. Hyp Translation Control Register
4.5.44. Virtualization Translation Control Register
4.5.45. Domain Access Control Register
4.5.46. Hyp System Trap Register
4.5.47. Hyp Auxiliary Configuration Register
4.5.48. Data Fault Status Register
4.5.49. Instruction Fault Status Register
4.5.50. Auxiliary Data Fault Status Register
4.5.51. Auxiliary Instruction Fault Status Register
4.5.52. Hyp Auxiliary Data Fault Status Syndrome Register
4.5.53. Hyp Auxiliary Instruction Fault Status Syndrome Register
4.5.54. Hyp Syndrome Register
4.5.55. Data Fault Address Register
4.5.56. Instruction Fault Address Register
4.5.57. Hyp Data Fault Address Register
4.5.58. Hyp Instruction Fault Address Register
4.5.59. Hyp IPA Fault Address Register
4.5.60. Physical Address Register
4.5.61. L2 Control Register
4.5.62. L2 Extended Control Register
4.5.63. Primary Region Remap Register
4.5.64. Memory Attribute Indirection Registers 0 and 1
4.5.65. Normal Memory Remap Register
4.5.66. Auxiliary Memory Attribute Indirection Register 0
4.5.67. Auxiliary Memory Attribute Indirection Register 1
4.5.68. Hyp Auxiliary Memory Attribute Indirection Register 0
4.5.69. Hyp Auxiliary Memory Attribute Indirection Register 1
4.5.70. Vector Base Address Register
4.5.71. Reset Management Register
4.5.72. Interrupt Status Register
4.5.73. Hyp Vector Base Address Register
4.5.74. FCSE Process ID Register
4.5.75. L2 Auxiliary Control Register
4.5.76. CPU Auxiliary Control Register
4.5.77. CPU Extended Control Register
4.5.78. CPU Memory Error Syndrome Register
4.5.79. L2 Memory Error Syndrome Register
4.5.80. Configuration Base Address Register
5. Memory Management Unit
5.1. About the MMU
5.2. TLB organization
5.2.1. Micro TLB
5.2.2. Main TLB
5.2.3. IPA cache RAM
5.2.4. Walk cache RAM
5.3. TLB match process
5.4. External aborts
5.4.1. External aborts on data read or write
6. Level 1 Memory System
6.1. About the L1 memory system
6.2. Cache behavior
6.2.1. Instruction cache disabled behavior
6.2.2. Instruction cache speculative memory accesses
6.2.3. Data cache disabled behavior
6.2.4. Data cache maintenance considerations
6.2.5. Data cache coherency
6.3. Support for v8 memory types
6.4. L1 Instruction memory system
6.4.1. Enabling program flow prediction
6.4.2. Program flow prediction
6.5. L1 Data memory system
6.5.1. Internal exclusive monitor
6.5.2. ACE transactions
6.5.3. CHI transactions
6.6. Data prefetching
6.6.1. Preload instructions
6.6.2. Data prefetching and monitoring
6.6.3. Non-temporal loads
6.6.4. Data Cache Zero
6.7. Direct access to internal memory
6.7.1. Data cache tag and data encoding
6.7.2. Instruction cache tag and data encoding
6.7.3. TLB RAM accesses
7. Level 2 Memory System
7.1. About the L2 memory system
7.2. Snoop Control Unit
7.2.1. Bus interface configuration signals
7.2.2. Snoop and maintenance requests
7.3. ACE master interface
7.3.1. Memory interface attributes
7.3.2. ACE transfers
7.3.3. Snoop channel properties
7.3.4. Read response
7.3.5. Write response
7.3.6. Barriers
7.3.7. AXI3 compatibility mode
7.3.8. AXI privilege information
7.4. CHI master interface
7.4.1. Memory interface attributes
7.4.2. CHI transfers
7.4.3. CHI channel properties
7.4.4. CHI transaction IDs
7.4.5. CHI nodes
7.5. Additional memory attributes
7.6. Optional integrated L2 cache
7.6.1. External aborts handling
7.7. ACP
7.7.1. Transfer size support
7.7.2. ACP user signals
7.7.3. ACP performance
8. Cache Protection
8.1. Cache protection behavior
8.2. Error reporting
9. Generic Interrupt Controller CPU Interface
9.1. About the GIC CPU Interface
9.1.1. Bypassing the CPU Interface
9.2. GIC programmers model
9.2.1. Memory map
9.2.2. CPU interface register summary
9.2.3. CPU interface register descriptions
9.2.4. Virtual interface control register summary
9.2.5. Virtual interface control register descriptions
9.2.6. Virtual CPU interface register summary
9.2.7. Virtual CPU interface register descriptions
10. Generic Timer
10.1. About the Generic Timer
10.2. Generic Timer functional description
10.3. Generic Timer register summary
10.3.1. AArch64 Generic Timer register summary
10.3.2. AArch32 Generic Timer register summary
11. Debug
11.1. About debug
11.1.1. Debug host
11.1.2. Protocol converter
11.1.3. Debug target
11.1.4. The debug unit
11.1.5. Self-hosted debug
11.2. Debug register interfaces
11.2.1. Processor interfaces
11.2.2. Effects of resets on debug registers
11.2.3. External access permissions
11.3. AArch64 debug register summary
11.4. AArch64 debug register descriptions
11.4.1. Debug Breakpoint Control Registers, EL1
11.4.2. Debug Watchpoint Control Registers, EL1
11.4.3. Debug Claim Tag Set register
11.5. AArch32 debug register summary
11.6. AArch32 debug register descriptions
11.6.1. Debug ID Register
11.6.2. Debug Device ID Register
11.6.3. Debug Device ID Register 1
11.7. Memory-mapped register summary
11.8. Memory-mapped register descriptions
11.8.1. External Debug Integration Mode Control Register
11.8.2. External Debug Device ID Register 0
11.8.3. External Debug Device ID Register 1
11.8.4. Peripheral Identification Registers
11.8.5. Component Identification Registers
11.9. Debug events
11.9.1. Watchpoint debug events
11.9.2. Debug OS Lock
11.10. External debug interface
11.10.1. Debug memory map
11.10.2. DBGPWRDUP debug signal
11.10.3. DBGL1RSTDISABLE debug signal
11.10.4. Changing the authentication signals
11.11. ROM table
11.11.1. ROM table register interface
11.11.2. ROM table register summary
11.11.3. ROM table register descriptions
11.11.4. Peripheral Identification Registers
11.11.5. Component Identification Registers
12. Performance Monitor Unit
12.1. About the PMU
12.2. PMU functional description
12.2.1. Event interface
12.2.2. System register and APB interface
12.2.3. Counters
12.2.4. PMU register interfaces
12.2.5. External register access permissions
12.3. AArch64 PMU register summary
12.4. AArch64 PMU register descriptions
12.4.1. Performance Monitors Control Register
12.4.2. Performance Monitors Common Event Identification Register 0
12.4.3. Performance Monitors Common Event Identification Register 1
12.5. AArch32 PMU register summary
12.6. AArch32 PMU register descriptions
12.6.1. Performance Monitors Control Register
12.6.2. Performance Monitors Common Event Identification Register 0
12.6.3. Performance Monitors Common Event Identification Register 1
12.7. Memory-mapped register summary
12.8. Memory-mapped register descriptions
12.8.1. Performance Monitor Configuration Register
12.8.2. Peripheral Identification Registers
12.8.3. Component Identification Registers
12.9. Events
12.10. Interrupts
12.11. Exporting PMU events
12.11.1. External hardware
12.11.2. Debug trace hardware
13. Embedded Trace Macrocell
13.1. About the ETM
13.2. ETM trace unit generation options and resources
13.3. ETM trace unit functional description
13.3.1. Processor interface
13.3.2. Trace generation
13.3.3. Filtering and triggering resources
13.3.4. FIFO
13.3.5. Trace out
13.3.6. Syncbridge
13.4. Reset
13.5. Modes of operation and execution
13.5.1. Controlling ETM trace unit programming
13.5.2. Programming and reading ETM trace unit registers
13.6. ETM trace unit register interfaces
13.6.1. Access permissions
13.7. ETM register summary
13.8. ETM register descriptions
13.8.1. Programming Control Register
13.8.2. Status Register
13.8.3. Trace Configuration Register
13.8.4. Branch Broadcast Control Register
13.8.5. Auxiliary Control Register
13.8.6. Event Control 0 Register
13.8.7. Event Control 1 Register
13.8.8. Stall Control Register
13.8.9. Global Timestamp Control Register
13.8.10. Synchronization Period Register
13.8.11. Cycle Count Control Register
13.8.12. Trace ID Register
13.8.13. ViewInst Main Control Register
13.8.14. ViewInst Include-Exclude Control Register
13.8.15. ViewInst Start-Stop Control Register
13.8.16. Sequencer State Transition Control Registers 0-2
13.8.17. Sequencer Reset Control Register
13.8.18. Sequencer State Register
13.8.19. External Input Select Register
13.8.20. Counter Reload Value Registers 0-1
13.8.21. Counter Control Register 0
13.8.22. Counter Control Register 1
13.8.23. Counter Value Registers 0-1
13.8.24. ID Register 8
13.8.25. ID Register 9
13.8.26. ID Register 10
13.8.27. ID Register 11
13.8.28. ID Register 12
13.8.29. ID Register 13
13.8.30. Implementation Specific Register 0
13.8.31. ID Register 0
13.8.32. ID Register 1
13.8.33. ID Register 2
13.8.34. ID Register 3
13.8.35. ID Register 4
13.8.36. ID Register 5
13.8.37. Resource Selection Control Registers 2-16
13.8.38. Single-Shot Comparator Control Register 0
13.8.39. Single-Shot Comparator Status Register 0
13.8.40. OS Lock Access Register
13.8.41. OS Lock Status Register
13.8.42. Power Down Control Register
13.8.43. Power Down Status Register
13.8.44. Address Comparator Value Registers 0-7
13.8.45. Address Comparator Access Type Registers 0-7
13.8.46. Context ID Comparator Value Register 0
13.8.47. VMID Comparator Value Register 0
13.8.48. Context ID Comparator Control Register 0
13.8.49. Integration ATB Identification Register
13.8.50. Integration Instruction ATB Data Register
13.8.51. Integration Instruction ATB In Register
13.8.52. Integration Instruction ATB Out Register
13.8.53. Integration Mode Control Register
13.8.54. Claim Tag Set Register
13.8.55. Claim Tag Clear Register
13.8.56. Device Affinity Register 0
13.8.57. Device Affinity Register 1
13.8.58. Software Lock Access Register
13.8.59. Software Lock Status Register
13.8.60. Authentication Status Register
13.8.61. Device Architecture Register
13.8.62. Device ID Register
13.8.63. Device Type Register
13.8.64. Peripheral Identification Registers
13.8.65. Component Identification Registers
13.9. Interaction with debug and performance monitoring unit
13.9.1. Interaction with the performance monitoring unit
13.9.2. Effect of debug double lock on trace register access
14. Cross Trigger
14.1. About the cross trigger
14.2. Trigger inputs and outputs
14.3. Cortex-A53 CTM
14.4. Cross trigger register summary
14.4.1. External register access permissions
14.5. Cross trigger register descriptions
14.5.1. CTI Device Identification Register
14.5.2. CTI Integration Mode Control Register
14.5.3. CTI Peripheral Identification Registers
14.5.4. Component Identification Registers
A. Signal Descriptions
A.1. About the signal descriptions
A.2. Clock signals
A.3. Reset signals
A.4. Configuration signals
A.5. Generic Interrupt Controller signals
A.6. Generic Timer signals
A.7. Power management signals
A.8. L2 error signals
A.9. ACE and CHI interface signals
A.10. CHI interface signals
A.10.1. Clock and configuration signals
A.10.2. Transmit request virtual channel signals
A.10.3. Transmit response virtual channel signals
A.10.4. Transmit data virtual channel signals
A.10.5. Receive snoop virtual channel signals
A.10.6. Receive response virtual channel signals
A.10.7. Receive data virtual channel signals
A.10.8. System address map signals
A.11. ACE interface signals
A.11.1. Clock and configuration signals
A.11.2. Write address channel signals
A.11.3. Write data channel signals
A.11.4. Write data response channel signals
A.11.5. Read address channel signals
A.11.6. Read data channel signals
A.11.7. Coherency address channel signals
A.11.8. Coherency response channel signals
A.11.9. Coherency data channel handshake signals
A.11.10. Read and write acknowledge signals
A.12. ACP interface signals
A.12.1. Clock and configuration signals
A.12.2. Write address channel signals
A.12.3. Write data channel signals
A.12.4. Write response channel signals
A.12.5. Read address channel signals
A.12.6. Read data channel signals
A.13. External debug interface
A.13.1. APB interface signals
A.13.2. Miscellaneous debug signals
A.14. ATB interface signals
A.15. Miscellaneous ETM trace unit signals
A.16. CTI interface signals
A.17. PMU interface signals
A.18. DFT and MBIST interface signals
A.18.1. DFT interface
A.18.2. MBIST interface
B. Cortex-A53 Processor AArch32 unpredictable Behaviors
B.1. Use of R15 by Instruction
B.2. unpredictable instructions within an IT Block
B.3. Load/Store accesses crossing page boundaries
B.3.1. Crossing a page boundary with different memory types or shareability attributes
B.3.2. Crossing a 4KB boundary with a Device (or Strongly-Ordered) accesses
B.4. ARMv8 Debug unpredictable behaviors
B.4.1. A32 BKPT instruction with condition code not AL
B.4.2. Address match breakpoint match only on second halfword of an instruction
B.4.3. Address matching breakpoint on A32 instruction with DBGBCRn.BAS=1100
B.4.4. Address match breakpoint match on T32 instruction at DBGBCRn+2 with DBGBCRn.BAS=1111
B.4.5. Address mismatch breakpoint match on T32 instruction at DBGBCRn +2 with DBGBCRn.BAS=1111
B.4.6. Other mismatch breakpoint matches any address in current mode and state
B.4.7. Mismatch breakpoint on branch to self
B.4.8. Link to nonexistent breakpoint or breakpoint that is not context-aware
B.4.9. DBGWCRn_EL1.MASK!=00000 and DBGWCRn_EL1.BAS!=11111111
B.4.10. Address-matching Vector catch on 32-bit T32 instruction at (vector-2)
B.4.11. Address-matching Vector catch on 32-bit T32 instruction at (vector+2)
B.4.12. Address-matching Vector catch and Breakpoint on same instruction
B.4.13. Address match breakpoint with DBGBCRn_EL1.BAS=0000
B.4.14. DBGWCRn_EL1.BAS specifies a non-contiguous set of bytes within a double-word
B.4.15. A32 HLT instruction with condition code not AL
B.4.16. Execute instruction at a given EL when the corresponding EDECCR bit is 1 and Halting is allowed
B.4.17. Unlinked Context matching and Address mismatch breakpoints taken to Abort mode
B.4.18. Vector catch on Data or Prefetch abort, and taken to Abort mode
B.4.19. H > N or H = 0 at Non-secure EL1 and EL0, including value read from PMCR_EL0.N
B.4.20. H > N or H = 0: value read back in MDCR_EL2.HPMN
B.4.21. P ≥ M and P ≠ 31: reads and writes of PMXEVTYPER_EL0 and PMXEVCNTR_EL0
B.4.22. P ≥ M and P ≠ 31: value read in PMSELR_EL0.SEL
B.4.23. P = 31: reads and writes of PMXEVCNTR_EL0
B.4.24. n ≥ M: Direct access to PMEVCNTRn_EL0 and PMEVTYPERn_EL0
B.4.25. Exiting Debug state while instruction issued through EDITR is in flight
B.4.26. Using memory-access mode with a non-word-aligned address
B.4.27. Access to memory-mapped registers mapped to Normal memory
B.4.28. Not word-sized accesses or (AArch64 only) doubleword-sized accesses
B.4.29. External debug write to register that is being reset
B.4.30. Accessing reserved debug registers
B.4.31. Clearing the clear-after-read EDPRSR bits when Core power domain is on, and DoubleLockStatus() is TRUE
B.5. Other unpredictable behaviors
B.5.1. CSSELR indicates a cache that is not implemented
B.5.2. HDCR.HPMN is set to 0, or to a value larger than PMCR.N
C. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Example Cortex-A53 processor configuration
2.1. Cortex-A53 processor block diagram
2.2. PCLKENDBG with CLKIN:PCLK ratio changing from 3:1 to 1:1
2.3. ACLKENM with CLKIN:ACLKM ratio changing from 3:1 to 1:1
2.4. ACLKENS with CLKIN:ACLKS ratio changing from 3:1 to 1:1
2.5. SCLKEN with CLKIN:SCLK ratio changing from 3:1 to 1:1
2.6. ATCLKEN with CLKIN:ATCLK ratio changing from 3:1 to 1:1
2.7. CNTCLKEN with CLKIN:CNTCLK ratio changing from 3:1 to 1:1
2.8. Power domains
2.9. CLREXMON request and acknowledge handshake
2.10. L2 Wait For Interrupt timing
2.11. STANDBYWFI[3:0] and STANDBYWFIL2 signals
3.1. ARMv8 security model when EL3 is using AArch64
3.2. ARMv8 security model when EL3 is using AArch32
4.1. MIDR_EL1 bit assignments
4.2. MPIDR_EL1 bit assignments
4.3. REVIDR_EL1 bit assignments
4.4. ID_PFR0_EL1 bit assignments
4.5. ID_PFR1_EL1 bit assignments
4.6. ID_DFR0_EL1 bit assignments
4.7. ID_MMFR0_EL1 bit assignments
4.8. ID_MMFR1_EL1 bit assignments
4.9. ID_MMFR2_EL1 bit assignments
4.10. ID_MMFR3_EL1 bit assignments
4.11. ID_ISAR0_EL1 bit assignments
4.12. ID_ISAR1_EL1 bit assignments
4.13. ID_ISAR2_EL1 bit assignments
4.14. ID_ISAR3_EL1 bit assignments
4.15. ID_ISAR4_EL1 bit assignments
4.16. ID_ISAR5_EL1 bit assignments
4.17. ID_AA64PFR0_EL1 bit assignments
4.18. ID_AA64DFR0_EL1 bit assignments
4.19. ID_AA64ISAR0_EL1 bit assignments
4.20. ID_AA64MMFR0_EL1 bit assignments
4.21. CCSIDR_EL1 bit assignments
4.22. CLIDR_EL1 bit assignments
4.23. CSSELR_EL1 bit assignments
4.24. CTR_EL0 bit assignments
4.25. DCZID_EL0 bit assignments
4.26. VPIDR_EL2 bit assignments
4.27. VMPIDR_EL2 bit assignments
4.28. SCTLR_EL1 bit assignments
4.29. ACTLR_EL2 bit assignments
4.30. ACTLR_EL3 bit assignments
4.31. CPACR_EL1 bit assignments
4.32. SCTLR_EL2 bit assignments
4.33. HCR_EL2 bit assignments
4.34. MDCR_EL2 bit assignments
4.35. CPTR_EL2 bit assignments
4.36. HSTR_EL2 bit assignments
4.37. SCTLR_EL3 bit assignments
4.38. SCR_EL3 bit assignments
4.39. SDER32_EL3 bit assignments
4.40. TTBR0_EL1 bit assignments
4.41. TTBR1_EL1 bit assignments
4.42. CPTR_EL3 bit assignments
4.43. MDCR_EL3 bit assignments
4.44. TCR_EL1 bit assignments
4.45. TCR_EL2 bit assignments
4.46. VTCR_EL2 bit assignments
4.47. DACR32_EL2 bit assignments
4.48. TTBR0_EL3 bit assignments
4.49. TCR_EL3 bit assignments
4.50. ESR_EL1 bit assignments
4.51. IFSR32_EL2 bit assignments for Short-descriptor translation table format
4.52. IFSR32_EL2 bit assignments for Long-descriptor translation table format
4.53. ESR_EL2 bit assignments
4.54. ESR_EL3 bit assignments
4.55. FAR_EL1 bit assignments
4.56. FAR_EL2 bit assignments
4.57. HPFAR_EL2 bit assignments
4.58. L2CTLR_EL1 bit assignments
4.59. L2ECTLR_EL1 bit assignments
4.60. L2ACTLR_EL1 bit assignments
4.61. FAR_EL3 bit assignments
4.62. PAR_EL1 pass bit assignments
4.63. PAR_El1 fail bit assignments
4.64. MAIR_EL1 bit assignments
4.65. VBAR_EL1 bit assignments
4.66. VBAR_EL2 bit assignments
4.67. VBAR_EL3 bit assignments
4.68. RVBAR_EL3 bit assignments
4.69. RMR_EL3 bit assignments
4.70. ISR_EL1 bit assignments
4.71. CPUACTLR_EL1 bit assignments
4.72. CPUECTLR_EL1 bit assignments
4.73. CPUMERRSR_EL1 bit assignments
4.74. L2MERRSR_EL1 bit assignments
4.75. CBAR_EL1 bit assignments
4.76. MIDR bit assignments
4.77. MPIDR bit assignments
4.78. REVIDR bit assignments
4.79. ID_PFR0 bit assignments
4.80. ID_PFR1 bit assignments
4.81. ID_DFR0 bit assignments
4.82. ID_MMFR0 bit assignments
4.83. ID_MMFR1 bit assignments
4.84. ID_MMFR2 bit assignments
4.85. ID_MMFR3 bit assignments
4.86. ID_ISAR0 bit assignments
4.87. ID_ISAR1 bit assignments
4.88. ID_ISAR2 bit assignments
4.89. ID_ISAR3 bit assignments
4.90. ID_ISAR4 bit assignments
4.91. ID_ISAR5 bit assignments
4.92. CCSIDR bit assignments
4.93. CLIDR bit assignments
4.94. CSSELR bit assignments
4.95. CTR bit assignments
4.96. VPIDR bit assignments
4.97. VMPIDR bit assignments
4.98. SCTLR bit assignments
4.99. ACTLR bit assignments
4.100. CPACR bit assignments
4.101. SCR bit assignments
4.102. SDER bit assignments
4.103. NSACR bit assignments
4.104. SDCR bit assignments
4.105. HACTLR bit assignments
4.106. HSCTLR bit assignments
4.107. HCR bit assignments
4.108. HCR2 bit assignments
4.109. HDCR bit assignments
4.110. HCPTR bit assignments
4.111. TTBR0 bit assignments, TTBCR.EAE is 0
4.112. TTBR0 bit assignments, TTBRC.EAE is 1
4.113. TTBR1 bit assignments, TTBCR.EAE is 0
4.114. TTBR1 bit assignments, TTBCR.EAE is 1
4.115. TTBCR bit assignments, TTBCR.EAE is 0
4.116. TTBCR bit assignments, TTBCR.EAE is 1
4.117. HTCR bit assignments
4.118. VTCR bit assignments
4.119. DACR bit assignments
4.120. HSTR bit assignments
4.121. DFSR bit assignments for Short-descriptor translation table format
4.122. DFSR bit assignments for Long-descriptor translation table format
4.123. IFSR bit assignments for Short-descriptor translation table format
4.124. IFSR bit assignments for Long-descriptor translation table format
4.125. HSR bit assignments
4.126. DFAR bit assignments
4.127. IFAR bit assignments
4.128. HDFAR bit assignments
4.129. HIFAR bit assignments
4.130. HPFAR bit assignments
4.131. L2CTLR bit assignments
4.132. L2ECTLR bit assignments
4.133. PRRR bit assignments
4.134. MAIR0 and MAIR1 bit assignments
4.135. NMRR bit assignments
4.136. RMR bit assignments
4.137. ISR bit assignments
4.138. HVBAR bit assignments
4.139. L2ACTLR bit assignments
4.140. CPUACTLR bit assignments
4.141. CPUECTLR bit assignments
4.142. CPUMERRSR bit assignments
4.143. L2MERRSR bit assignments
4.144. CBAR bit assignments
9.1. GICC_IIDR bit assignments
9.2. GICH_VTR bit assignments
10.1. Architectural counter interface
11.1. Typical debug system
11.2. DBGBCRn_EL1 bit assignments
11.3. DBGWCRn_EL1 bit assignments
11.4. DBGCLAIMSET_EL1 bit assignments
11.5. DBGDIDR bit assignments
11.6. DBGDEVID bit assignments
11.7. DBGDEVID1 bit assignments
11.8. EDITCTRL bit assignments
11.9. EDDEVID bit assignments
11.10. EDDEVID1 bit assignments
11.11. EDPIDR0 bit assignments
11.12. EDPIDR1 bit assignments
11.13. EDPIDR2 bit assignments
11.14. EDPIDR3 bit assignments
11.15. EDPIDR4 bit assignments
11.16. EDCIDR0 bit assignments
11.17. EDCIDR1 bit assignments
11.18. EDCIDR2 bit assignments
11.19. EDCIDR3 bit assignments
11.20. External debug interface, including APBv3 slave port
11.21. ROMENTRY bit assignments
11.22. ROMPIDR0 bit assignments
11.23. ROMPIDR1 bit assignments
11.24. ROMPIDR2 bit assignments
11.25. ROMPIDR3 bit assignments
11.26. ROMPIDR4 bit assignments
11.27. ROMCIDR0 bit assignments
11.28. ROMCIDR1 bit assignments
11.29. ROMCIDR2 bit assignments
11.30. ROMCIDR3 bit assignments
12.1. PMU block diagram
12.2. PMCR_EL0 bit assignments
12.3. PMCEID0_EL0 bit assignments
12.4. PMCEID1 bit assignments
12.5. PMCR bit assignments
12.6. PMCEID0 bit assignments
12.7. PMCEID1 bit assignments
12.8. PMCFGR bit assignments
12.9. PMPIDR0 bit assignments
12.10. PMPIDR1 bit assignments
12.11. PMPIDR2 bit assignments
12.12. PMPIDR3 bit assignments
12.13. PMPIDR4 bit assignments
12.14. PMCIDR0 bit assignments
12.15. PMCIDR1 bit assignments
12.16. PMCIDR2 bit assignments
12.17. PMCIDR3 bit assignments
13.1. ETM functional blocks
13.2. Programming ETM trace unit registers
13.3. TRCPRGCTLR bit assignments
13.4. TRCSTATR bit assignments
13.5. TRCCONFIGR bit assignments
13.6. TRCBBCTLR bit assignments
13.7. TRCAUXCTLR bit assignments
13.8. TRCEVENTCL0R bit assignments
13.9. TRCEVENTCL1R bit assignments
13.10. TRCSTALLCTLR bit assignments
13.11. TRCTSCTLR bit assignments
13.12. TRCSYNCPR bit assignments
13.13. TRCCCCTLR bit assignments
13.14. TRCTRACEIDR bit Assignments
13.15. TRCVICTLR bit assignments
13.16. TRCVIIECTLR bit assignments
13.17. TRCVISSCTLR bit assignments
13.18. TRCSEQEVRn bit assignments
13.19. TRCSEQRSTEVR bit assignments
13.20. TRCSEQSTR bit assignments
13.21. TRCEXTINSELR bit assignments
13.22. TRCCNTRLDVRn bit assignments
13.23. TRCCNTCTLR0 bit assignments
13.24. TRCCNTCTLR1 bit assignments
13.25. TRCCNTVRn bit assignments
13.26. TRCIDR8 bit assignments
13.27. TRCID9 bit assignments
13.28. TRCIDR10 bit assignments
13.29. TRCIDR11 bit assignments
13.30. TRCIDR12 bit assignments
13.31. TRCIDR13 bit assignments
13.32. TRCIMSPEC0 bit assignments
13.33. TRCIDR0 bit assignments
13.34. TRCIDR1 bit assignments
13.35. TRCIDR2 bit assignments
13.36. TRCIDR3 bit assignments
13.37. TRCIDR4 bit assignments
13.38. TRCIDR5 bit assignments
13.39. TRCRSCTLRn bit assignments
13.40. TRCSSCCR0 bit assignments
13.41. TRCSSCSR0 bit assignments
13.42. TRCOSLAR bit assignments
13.43. TRCOSLSR bit assignments
13.44. TRCPDCR bit assignments
13.45. TRCPDSR bit assignments
13.46. TRCACVRn bit assignments
13.47. TRCACATRn bit assignments
13.48. TRCCIDCVR0 bit assignments
13.49. TRCVMIDCVR0 bit assignments
13.50. TRCCIDCCTLR0 bit assignments
13.51. TRCITATBIDR bit assignments
13.52. TRCITIDATAR bit assignments
13.53. TRCITIATBINR bit assignments
13.54. TRCITIATBOUTR bit assignments
13.55. TRCITCTRL bit assignments
13.56. TRCCLAIMSET bit assignments
13.57. TRCCLAIMCLR bit assignments
13.58. TRCDEVAFF0 bit assignments
13.59. TRCLAR bit assignments
13.60. TRCLSR bit assignments
13.61. TRCAUTHSTATUS bit assignments
13.62. TRCDEVARCH bit assignments
13.63. TRCDEVID bit assignments
13.64. TRCDEVTYPE bit assignments
13.65. TRCPIDR0 bit assignments
13.66. TRCPIDR1 bit assignments
13.67. TRCPIDR2 bit assignments
13.68. TRCPIDR3 bit assignments
13.69. TRCPIDR4 bit assignments
13.70. TRCCIDR0 bit assignments
13.71. TRCCIDR1 bit assignments
13.72. TRCCIDR2 bit assignments
13.73. TRCCIDR3 bit assignments
14.1. Debug system components
14.2. CTIDEVID bit assignments
14.3. CTIITCTRL bit assignments
14.4. CTIPIDR0 bit assignments
14.5. CTIPIDR1 bit assignments
14.6. CTIPIDR2 bit assignments
14.7. CTIPIDR3 bit assignments
14.8. CTIPIDR4 bit assignments
14.9. CTICIDR0 bit assignments
14.10. CTICIDR1 bit assignments
14.11. CTICIDR2 bit assignments
14.12. CTICIDR3 bit assignments

List of Tables

1. Typographical conventions
1.1. Cortex-A53 processor implementation options
2.1. Valid reset combinations
2.2. Power domain description
2.3. Power state description
2.4. Supported processor power states
2.5. Supported core power states
3.1. CPSR J and T bit encoding
3.2. AArch64 stack pointer options
3.3. AArch32 processor modes and associated exception levels
4.1. AArch64 identification registers
4.2. AArch64 exception handling registers
4.3. AArch64 virtual memory control registers
4.4. AArch64 other system control registers
4.5. AArch64 performance monitor registers
4.6. AArch64 reset management registers
4.7. AArch64 security registers
4.8. AArch64 virtualization registers
4.9. GIC system registers
4.10. AArch64 miscellaneous system control operations
4.11. AArch64 implementation defined registers
4.12. AArch64 address translation register
4.13. MIDR_EL1 bit assignments
4.14. MIDR_EL1 access encoding
4.15. MPIDR_EL1 bit assignments
4.16. MPIDR access encoding
4.17. REVIDR_EL1 bit assignments
4.18. REVIDR_EL1 access encoding
4.19. ID_PFR0_EL1 bit assignments
4.20. REVIDR access encoding
4.21. ID_PFR1_EL1 bit assignments
4.22. REVIDR access encoding
4.23. ID_DFR0_EL1 bit assignments
4.24. REVIDR access encoding
4.25. ID_MMFR0_EL1 bit assignments
4.26. ID_MMFR0_EL1 access encoding
4.27. ID_MMFR1_EL1 bit assignments
4.28. ID_MMFR1_EL1 access encoding
4.29. ID_MMFR2_EL1 bit assignments
4.30. ID_MMFR2_EL1 access encoding
4.31. ID_MMFR3_EL1 bit assignments
4.32. ID_MMFR3_EL1 access encoding
4.33. ID_ISAR0_EL1 bit assignments
4.34. ID_ISAR0_EL1 access encoding
4.35. ID_ISAR1_EL1 bit assignments
4.36. ID_ISAR1_EL1 access encoding
4.37. ID_ISAR2_EL1 bit assignments
4.38. ID_ISAR2_EL1 access encoding
4.39. ID_ISAR3_EL1 bit assignments
4.40. ID_ISAR3_EL1 access encoding
4.41. ID_ISAR4_EL1 bit assignments
4.42. ID_ISAR4_EL1 access encoding
4.43. ID_ISAR5_EL1 bit assignments
4.44. ID_ISAR5_EL1 access encoding
4.45. ID_AA64PFR0_EL1 bit assignments
4.46. ID_AA64PFR0_EL1 access encoding
4.47. ID_AA64DFR0_EL1 bit assignments
4.48. ID_AA64DFR0_EL1 access encoding
4.49. ID_AA64ISAR0_EL1 bit assignments
4.50. ID_AA64ISAR0_EL1 access encoding
4.51. ID_AA64MMFR0_EL1 bit assignments
4.52. ID_AA64MMFR0_EL1 access encoding
4.53. CCSIDR_EL1 bit assignments
4.54. CCSIDR_EL1 access encoding
4.55. CLIDR_EL1 bit assignments
4.56. CLIDR_EL1 access encoding
4.57. CSSELR_EL1 bit assignments
4.58. CSSELR_EL1 access encoding
4.59. CTR_EL0 bit assignments
4.60. CTR_EL0 access encoding
4.61. DCZID_EL0 bit assignments
4.62. DCZID_EL0 access encoding
4.63. VPIDR_EL2 bit assignments
4.64. VPIDR_EL2 access encoding
4.65. VMPIDR_EL2 bit assignments
4.66. VMPIDR_EL2 access encoding
4.67. SCTLR_EL1 bit assignments
4.68. ACTLR_EL2 bit assignments
4.69. ACTLR_EL3 bit assignments
4.70. CPACR_EL1 bit assignments
4.71. SCTLR_EL2 bit assignments
4.72. HCR_EL2 bit assignments
4.73. MDCR_EL2 bit assignments
4.74. CPTR_EL2 bit assignments
4.75. HSTR_EL2 bit assignments
4.76. SCTLR_EL3 bit assignments
4.77. SCR_EL3 bit assignments
4.78. SDER32_EL3 bit assignments
4.79. TTBR0_EL1 bit assignments
4.80. TTBR1_EL1 bit assignments
4.81. CPTR_EL3 bit assignments
4.82. MDCR_EL3 bit assignments
4.83. TCR_EL1 bit assignments
4.84. TCR_EL2 bit assignments
4.85. VTCR_EL2 bit assignments
4.86. DACR32_EL2 bit assignments
4.87. TTBR0_EL3 bit assignments
4.88. TCR_EL3 bit assignments
4.89. ESR_EL1 bit assignments
4.90. IFSR32_EL2 bit assignments for Short-descriptor translation table format
4.91. IFSR32_EL2 bit assignments for Long-descriptor translation table format
4.92. Encodings of LL bits associated with the MMU fault
4.93. IFSR32_EL2 access encoding
4.94. ESR_EL2 bit assignments
4.95. ESR_EL3 bit assignments
4.96. FAR_EL1 bit assignments
4.97. FAR_EL2 bit assignments
4.98. HPFAR_EL2 bit assignments
4.99. L2CTLR_EL1 bit assignments
4.100. L2ECTLR_EL1 bit assignments
4.101. L2ACTLR_EL1 bit assignments
4.102. FAR_EL3 bit assignments
4.103. PAR_EL1 pass bit assignments
4.104. PAR_EL1 fail bit assignments
4.105. Attr<n>[7:4] bit assignments
4.106. Attr<n>[3:0] bit assignments
4.107. Encoding of R and W bits in some Attrm fields
4.108. VBAR_EL1 bit assignments
4.109. VBAR_EL2 bit assignments
4.110. VBAR_EL2 access encoding
4.111. VBAR_EL3 bit assignments
4.112. RVBAR_EL3 bit assignments
4.113. RMR_EL3 bit assignments
4.114. ISR_EL1 bit assignments
4.115. ISR_EL1 access encoding
4.116. CPUACTLR_EL1 bit assignments
4.117. CPUECTLR_EL1 bit assignments
4.118. CPUMERRSR_EL1 bit assignments
4.119. L2MERRSR_EL1 bit assignments
4.120. CBAR_EL1 bit assignments
4.121. System register field values
4.122. c0 register summary
4.123. c1 register summary
4.124. c2 register summary
4.125. c3 register summary
4.126. c3 register summary
4.127. c5 register summary
4.128. c6 register summary
4.129. c7 register summary
4.130. c9 register summary
4.131. c10 register summary
4.132. c12 register summary
4.133. c13 register summary
4.134. c14 register summary
4.135. c15 register summary
4.136. 64-bit register summary
4.137. Identification registers
4.138. Virtual memory control registers
4.139. Fault handling registers
4.140. Other system registers
4.141. Address translation operations
4.142. Miscellaneous System instructions
4.143. Performance monitor registers
4.144. Security registers
4.145. Virtualization registers
4.146. AArch32 GIC system registers
4.147. Memory access registers
4.148. MIDR bit assignments
4.149. MPIDR access encoding
4.150. MPIDR bit assignments
4.151. MPIDR access encoding
4.152. REVIDR bit assignments
4.153. REVIDR access encoding
4.154. ID_PFR0 bit assignments
4.155. ID_PFR0 access encoding
4.156. ID_PFR1 bit assignments
4.157. ID_PFR1 access encoding
4.158. ID_DFR0 bit assignments
4.159. ID_DFR0 access encoding
4.160. ID_MMFR0 bit assignments
4.161. ID_MMFR0 access encoding
4.162. ID_MMFR1 bit assignments
4.163. ID_MMFR1 access encoding
4.164. ID_MMFR2 bit assignments
4.165. ID_MMFR2 access encoding
4.166. ID_MMFR3 bit assignments
4.167. ID_MMFR3 access encoding
4.168. ID_ISAR0 bit assignments
4.169. ID_ISAR0 access encoding
4.170. ID_ISAR1 bit assignments
4.171. ID_ISAR1 access encoding
4.172. ID_ISAR2 bit assignments
4.173. ID_ISAR2 access encoding
4.174. ID_ISAR3 bit assignments
4.175. ID_ISAR3 access encoding
4.176. ID_ISAR4 bit assignments
4.177. ID_ISAR4 access encoding
4.178. ID_ISAR5 bit assignments
4.179. ID_ISAR5 access encoding
4.180. CCSIDR bit assignments
4.181. CCSIDR encodings
4.182. CCSIDR access encoding
4.183. CLIDR bit assignments
4.184. CLIDR access encoding
4.185. CSSELR bit assignments
4.186. CSSELR access encoding
4.187. CTR bit assignments
4.188. CTR access encoding
4.189. VPIDR bit assignments
4.190. VPIDR access encoding
4.191. VMPIDR bit assignments
4.192. VMPIDR access encoding
4.193. SCTLR bit assignments
4.194. ACTLR bit assignments
4.195. CPACR bit assignments
4.196. SCR bit assignments
4.197. SDER bit assignments
4.198. NSACR bit assignments
4.199. SDCR bit assignments
4.200. HACTLR bit assignments
4.201. HSCTLR bit assignments
4.202. HCR bit assignments
4.203. HCR2 bit assignments
4.204. HDCR bit assignments
4.205. HCPTR bit assignments
4.206. TTBR0 bit assignments, TTBCR.EAE is 0
4.207. TTBR0 bit assignments, TTBRC.EAE is 1
4.208. TTBR1 bit assignments, TTBCR.EAE is 0
4.209. TTBR1 bit assignments, TTBCR.EAE is 1
4.210. TTBCR bit assignments, TTBCR.EAE is 0
4.211. TTBCR bit assignments, TTBCR.EAE is 1
4.212. HTCR bit assignments
4.213. VTCR bit assignments
4.214. DACR bit assignments
4.215. HSTR bit assignments
4.216. DFSR bit assignments for Short-descriptor translation table format
4.217. DFSR bit assignments for Long-descriptor translation table format
4.218. Encodings of LL bits associated with the MMU fault
4.219. IFSR bit assignments for Short-descriptor translation table format
4.220. IFSR bit assignments for Long-descriptor translation table format
4.221. Encodings of LL bits associated with the MMU fault
4.222. IFSR access encoding
4.223. HSR bit assignments
4.224. DFAR bit assignments
4.225. IFAR bit assignments
4.226. HDFAR bit assignments
4.227. HIFAR bit assignments
4.228. HPFAR bit assignments
4.229. L2CTLR bit assignments
4.230. L2ECTLR bit assignments
4.231. PRRR bit assignments
4.232. Memory attributes and the n value for the PRRR field descriptions
4.233. MAIR0 and MAIR1 bit assignments
4.234. Attr<n>[7:4] bit assignments
4.235. Attr<n>[3:0] bit assignments
4.236. Encoding of R and W bits in some Attrm fields
4.237. NMRR bit assignments
4.238. RMR bit assignments
4.239. ISR access encoding
4.240. ISR bit assignments
4.241. ISR access encoding
4.242. HVBAR bit assignments
4.243. L2ACTLR bit assignments
4.244. CPUACTLR bit assignments
4.245. CPUECTLR bit assignments
4.246. CPUMERRSR bit assignments
4.247. L2MERRSR bit assignments
4.248. CBAR bit assignments
6.1. ARMv8 memory types
6.2. ACE transactions
6.3. CHI transactions
6.4. AArch64 registers used to access internal memory
6.5. AArch32 CP15 registers used to access internal memory
6.6. Data cache tag and data location encoding
6.7. Data cache tag data format
6.8. MOESI state
6.9. Instruction cache tag and data location encoding
6.10. Instruction cache tag data format
6.11. TLB Data Read Operation Register location encoding
6.12. TLB RAM format
6.13. Main TLB descriptor data fields
6.14. Main TLB memory types and shareability
6.15. Walk cache descriptor fields
6.16. IPA cache descriptor fields
7.1. Supported ACE configurations
7.2. Supported features in the ACE configurations
7.3. Supported CHI configurations
7.4. Supported features in the CHI configurations
7.5. ACE master interface attributes
7.6. Encodings for AWIDM[4:0]
7.7. Encodings for ARIDM[5:0]
7.8. ACE transactions
7.9. ACE channel properties
7.10. Cortex-A53 MPCore mode and ARPROT and AWPROT values
7.11. CHI master interface attributes
7.12. CHI transactions
7.13. CHI channel properties
7.14. CHI transactions
7.15. Memory attribute bus encodings
7.16. Shareability attribute encoding
8.1. Cache protection behavior
9.1. Memory Map
9.2. CPU interface register summary
9.3. Active Priority Register implementation
9.4. GICC_IIDR bit assignments
9.5. Virtual interface control register summary
9.6. GICH_VTR bit assignments
9.7. Virtual CPU interface register summary
10.1. Generic Timer signals
10.2. AArch64 Generic Timer registers
10.3. AArch32 Generic Timer registers
11.1. External register conditions
11.2. External register condition code example
11.3. AArch64 debug register summary
11.4. DBGBCRn_EL1 bit assignments
11.5. DBGWCRn_EL1 bit assignments
11.6. DBGCLAIMSET_EL1 bit assignments
11.7. AArch32 debug register summary
11.8. DBGDIDR bit assignments
11.9. DBGDEVID bit assignments
11.10. DBGDEVID1 bit assignments
11.11. Memory-mapped debug register summary
11.12. EDITCTRL bit assignments
11.13. EDDEVID bit assignments
11.14. EDDEVID1 bit assignments
11.15. Summary of the Peripheral Identification Registers
11.16. EDPIDR0 bit assignments
11.17. EDPIDR1 bit assignments
11.18. EDPIDR2 bit assignments
11.19. EDPIDR3 bit assignments
11.20. EDPIDR4 bit assignments
11.21. Summary of the Component Identification Registers
11.22. EDCIDR0 bit assignments
11.23. EDCIDR1 bit assignments
11.24. EDCIDR2 bit assignments
11.25. EDCIDR3 bit assignments
11.26. Address mapping for APB components
11.27. Address mapping for APB components
11.28. ROM table registers
11.29. ROMENTRY bit assignments
11.30. v8 ROMENTRY values
11.31. Legacy v7 ROMENTRY values
11.32. Summary of the ROM table Peripheral Identification Registers
11.33. ROMPIDR0 bit assignments
11.34. ROMPIDR1 bit assignments
11.35. ROMPIDR2 bit assignments
11.36. ROMPIDR3 bit assignments
11.37. ROMPIDR4 bit assignments
11.38. Summary of the ROM table component Identification registers
11.39. ROMCIDR0 bit assignments
11.40. ROMCIDR1 bit assignments
11.41. ROMCIDR2 bit assignments
11.42. ROMCIDR3 bit assignments
12.1. External register conditions
12.2. External register condition code example
12.3. PMU register summary in the AArch64 Execution state
12.4. PMCR_EL0 bit assignments
12.5. PMCEID0_EL0 bit assignments
12.6. PMU common events
12.7. PMCEID1 bit assignments
12.8. PMU common events
12.9. PMU register summary in the AArch32 Execution state
12.10. PMCR bit assignments
12.11. PMCEID0 bit assignments
12.12. PMU events
12.13. PMCEID1 bit assignments
12.14. PMU common events
12.15. Memory-mapped PMU register summary
12.16. PMCFGR bit assignments
12.17. Summary of the Peripheral Identification Registers
12.18. PMPIDR0 bit assignments
12.19. PMPIDR1 bit assignments
12.20. PMPIDR2 bit assignments
12.21. PMPIDR3 bit assignments
12.22. PMPIDR4 bit assignments
12.23. Summary of the Component Identification Registers
12.24. PMCIDR0 bit assignments
12.25. PMCIDR1 bit assignments
12.26. PMCIDR2 bit assignments
12.27. PMCIDR3 bit assignments
12.28. PMU events
13.1. ETM trace unit generation options implemented
13.2. ETM trace unit resources implemented
13.3. ETM trace unit register summary
13.4. TRCPRGCTLR bit assignments
13.5. TRCSTATR bit assignments
13.6. TRCCONFIGR bit assignments
13.7. TRCBBCTLR bit assignments
13.8. TRCAUXCTLR bit assignments
13.9. TRCEVENTCTL0R bit assignments
13.10. TRCEVENTCL1R bit assignments
13.11. TRCSTALLCTLR bit assignments
13.12. TRCTSCTLR bit assignments
13.13. TRCSYNCPR bit assignments
13.14. TRCCCCTLR bit assignments
13.15. TRCTRACEIDR bit assignments
13.16. TRCVICTLR bit assignments
13.17. TRCVIIECTLR bit assignments
13.18. TRCVISSCTLR bit assignments
13.19. TRCSEQEVRn bit assignments
13.20. TRCSEQRSTEVR bit assignments
13.21. TRCSEQSTR bit assignments
13.22. TRCEXTINSELR bit assignments
13.23. TRCCNTRLDVRn bit assignments
13.24. TRCCNTCTLR0 bit assignments
13.25. TRCCNTCTLR1 bit assignments
13.26. TRCCNTVRn bit assignments
13.27. TRCIDR8 bit assignments
13.28. TRCID9 bit assignments
13.29. TRCID10 bit assignments
13.30. TRCID11 bit assignments
13.31. TRCID12 bit assignments
13.32. TRCID13 bit assignments
13.33. TRCIMSPEC0 bit assignments
13.34. TRCIDR0 bit assignments
13.35. TRCIDR1 bit assignments
13.36. TRCIDR2 bit assignments
13.37. TRCIDR3 bit assignments
13.38. TRCIDR4 bit assignments
13.39. TRCIDR5 bit assignments
13.40. TRCSCTLRn bit assignments
13.41. TRCSSCCR0 bit assignments
13.42. TRCSSCSR0 bit assignments
13.43. TRCOSLAR bit assignments
13.44. TRCOSLSR bit assignments
13.45. TRCPDCR bit assignments
13.46. TRCPDSR bit assignments
13.47. TRCACVRn bit assignments
13.48. TRCACATRn bit assignments
13.49. TRCCIDCVR0 bit assignments
13.50. TRCVMIDCVR0 bit assignments
13.51. TRCCIDCCTLR0 bit assignments
13.52. TRCITATBIDR bit assignments
13.53. TRCITIDATAR bit assignments
13.54. TRCITIATBINR bit assignments
13.55. TRCITIATBOUTR bit assignments
13.56. TRCITCTRL bit assignments
13.57. TRCCLAIMSET bit assignments
13.58. TRCCLAIMCLR bit assignments
13.59. TRCDEVAFF0 bit assignments
13.60. TRCDEVAFF0 access encoding
13.61. TRCLAR bit assignments
13.62. TRCLSR bit assignments
13.63. TRCAUTHSTATUS bit assignments
13.64. TRCDEVARCH bit assignments
13.65. TRCDEVID bit assignments
13.66. TRCDEVTYPE bit assignments
13.67. Summary of the Peripheral ID Registers
13.68. TRCPIDR0 bit assignments
13.69. TRCPIDR1 bit assignments
13.70. TRCPIDR2 bit assignments
13.71. TRCPIDR3 bit assignments
13.72. TRCPIDR4 bit assignments
13.73. Summary of the Component Identification Registers
13.74. TRCCIDR0 bit assignments
13.75. TRCCIDR1 bit assignments
13.76. TRCCIDR2 bit assignments
13.77. TRCCIDR3 bit assignments
14.1. Trigger inputs
14.2. Trigger outputs
14.3. Cross trigger register summary
14.4. External register conditions
14.5. External register condition code example
14.6. CTIDEVID bit assignments
14.7. CTIITCTRL bit assignments
14.8. Summary of the Peripheral Identification Registers
14.9. CTIPIDR0 bit assignments
14.10. CTIPIDR1 bit assignments
14.11. CTI PIDR2 bit assignments
14.12. CTIPIDR3 bit assignments
14.13. CTIPIDR4 bit assignments
14.14. Summary of the Component Identification Registers
14.15. CTICIDR0 bit assignments
14.16. CTICIDR1 bit assignments
14.17. CTICIDR2 bit assignments
14.18. CTICIDR3 bit assignments
A.1. Clock signal
A.2. Reset and reset control signals
A.3. Configuration signals
A.4. GIC signals
A.5. Generic Timer signals
A.6. Non-Retention power management signals
A.7. Retention power management signals
A.8. L2 error signals
A.9. ACE and CHI interface signals
A.10. Clock and configuration signals
A.11. Transmit request virtual channel signals
A.12. Transmit response virtual channel signals
A.13. Transmit data virtual channel signals
A.14. Receive snoop virtual channel signals
A.15. Receive response virtual channel signals
A.16. Receive Data virtual channel signals
A.17. System address map signals
A.18. Clock and configuration signals
A.19. Write address channel signals
A.20. Write data channel signals
A.21. Write data response channel signals
A.22. Read address channel signals
A.23. Read data channel signals
A.24. Coherency address channel signals
A.25. Coherency response channel signals
A.26. Coherency data channel handshake signals
A.27. Read and write acknowledge signals
A.28. Clock and Configuration signals
A.29. Write address channel signals
A.30. Write data channel signals
A.31. Write response channel signals
A.32. Read address channel signals
A.33. Read data channel signals
A.34. APB interface signals
A.35. Miscellaneous Debug signals
A.36. ATB interface signals
A.37. Miscellaneous ETM trace unit signals
A.38. CTI interface signals
A.39. PMU interface signals
A.40. DFT interface signals
A.41. MBIST interface signals
C.1. Issue A
C.2. Differences between Issue A and Issue B
C.3. Differences between Issue B and Issue C
C.4. Differences between Issue C and Issue D

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

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Revision History
Revision A09 August 2013Release for r0p0
Revision B05 November 2013Release for r0p1
Revision C10 January 2014Release for r0p2
Revision D14 February 2014Second release for r0p2
Copyright © 2013-2014 ARM. All rights reserved.ARM DDI 0500D
Non-ConfidentialID021414