4.3.76. Reset Management Register

The RMR_EL3 characteristics are:

Purpose

Controls the execution state that the processor boots into and allows request of a warm reset.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

----RWRW
Configurations

The RMR_EL3 is architecturally mapped to the AArch32 RMR register.

Attributes

RMR_EL3 is a 32-bit register.

Figure 4.69 shows the RMR_EL3 bit assignments.

Figure 4.69. RMR_EL3 bit assignments

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Table 4.121 shows the RMR_EL3 bit assignments.

Table 4.121. RMR_EL3 bit assignments

BitsNameFunction
[31:2]-

Reserved, res0.

[1]RR

Reset Request. The possible values are:

0

This is the reset value.

1

Requests a warm reset. This bit is set to 0 by either a cold or warm reset.

The bit is strictly a request.

[0]AA64[a]

Determines which execution state the processor boots into after a warm reset. The possible values are:

0

AArch32 Execution state.

1

AArch64 Execution state.

The reset vector address on reset takes a choice between two values, depending on the value in the AA64 bit. This ensures that even with reprogramming of the AA64 bit, it is not possible to change the reset vector to go to a different location.

[a] The cold reset value depends on the AA64nAA32 signal.


To access the RMR_EL3:

MRS <Xt>, RMR_EL3 ; Read RMR_EL3 into Xt
MSR RMR_EL3, <Xt> ; Write Xt to RMR_EL3
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