Arm Cortex-A53 MPCore Processor Technical Reference Manual: 4.3.32. Auxiliary Control Register, EL2

4.3.32. Auxiliary Control Register, EL2

The ACTLR_EL2 characteristics are:

Purpose

Controls write access to implementation defined registers in Non-secure EL1 modes, such as CPUACTLR, CPUECTLR, L2CTLR, L2ECTLR and L2ACTLR.

Usage constraints

This register is accessible as follows:

EL0	EL1 (NS)	EL1 (S)	EL2	EL3 (SCR.NS = 1)	EL3 (SCR.NS = 0)
-	-	-	RW	RW	RW

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

Configurations

The ACTLR_EL2 is architecturally mapped to the AArch32 HACTLR register. See Hyp Auxiliary Control Register.

Attributes

ACTLR_EL2 is a 32-bit register.

Figure 4.29 shows the ACTLR_EL2 bit assignments.

Figure 4.29. ACTLR_EL2 bit assignments

Table 4.73 shows the ACTLR_EL2 bit assignments.

Table 4.73. ACTLR_EL2 bit assignments

Bits	Name	Function
[31:7]	-	Reserved, res0.
[6]	L2ACTLR_EL1 access control	L2ACTLR_EL1 write access control. The possible values are: `0` The register is not write accessible from Non-secure EL1.This is the reset value. `1` The register is write accessible from Non-secure EL1. Write access from Non-secure EL1 also requires ACTLR_EL3[6] to be set.
[5]	L2ECTLR_EL1 access control	L2ECTLR_EL1 write access control. The possible values are: `0` The register is not write accessible from Non-secure EL1.This is the reset value. `1` The register is write accessible from Non-secure EL1. Write access from Non-secure EL1 also requires ACTLR_EL3[5] to be set.
[4]	L2CTLR_EL1 access control	L2CTLR_EL1 write access control. The possible values are: `0` The register is not write accessible from Non-secure EL1.This is the reset value. `1` The register is write accessible from Non-secure EL1. Write access from Non-secure EL1 also requires ACTLR_EL3[4] to be set.
[3:2]	-	Reserved, res0.
[1]	CPUECTLR_EL1 access control	CPUECTLR_EL1 write access control. The possible values are: `0` The register is not write accessible from Non-secure EL1.This is the reset value. `1` The register is write accessible from Non-secure EL1. Write access from Non-secure EL1 also requires ACTLR_EL3[1] to be set.
[0]	CPUACTLR_EL1 access control	CPUACTLR_EL1 write access control. The possible values are: `0` The register is not write accessible from Non-secure EL1.This is the reset value. `1` The register is write accessible from Non-secure EL1. Write access from Non-secure EL1 also requires ACTLR_EL3[0] to be set.

To access the ACTLR_EL2:

MRS <Xt>, ACTLR_EL2 ; Read ACTLR_EL2 into Xt
MSR ACTLR_EL2, <Xt> ; Write Xt to ACTLR_EL2

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