2.4. AArch32 register summary

Table 2.15 gives a summary of the Cortex-A53 processor Advanced SIMD and Floating-point system registers in the AArch32 execution state.

Table 2.15. AArch32 Advanced SIMD and Floating-point system registers


Note

The Floating-Point Instruction Registers, FPINST and FPINST2 are not implemented, and any attempt to access them is unpredictable.

See the ARM® Architecture Reference Manual, ARMv8 for information on permitted accesses to the Advanced SIMD and Floating-point system registers.

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