2.3.3. Media and Floating-point Feature Register 0

The MVFR0_EL1 characteristics are:

Purpose

Describes the features provided by the Advanced SIMD and Floating-point Extension.

Usage constraints

This register is accessible as follows:

EL0EL1(NS)EL1(S)EL2EL3 (SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

MVFR0_EL1 is architecturally mapped to AArch32 register MVFR0. See Media and Floating-point Feature Register 0.

Attributes

MVFR0_EL1 is a 32-bit register.

Figure 2.3 shows the MVFR0_EL1 bit assignments.

Figure 2.3. MVFR0_EL1 bit assignments

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Table 2.7 shows the MVFR0_EL1 bit assignments.

Table 2.7. MVFR0_EL1 bit assignments 

BitsNameFunction
[31:28]FPRound

Indicates the rounding modes supported by the floating-point hardware:

0x1

All rounding modes supported.

[27:24]FPShVec

Indicates the hardware support for floating-point short vectors:

0x0

Not supported.

[23:20]FPSqrt

Indicates the hardware support for floating-point square root operations:

0x1

Supported.

[19:16]FPDivide

Indicates the hardware support for floating-point divide operations:

0x1

Supported.

[15:12]FPTrap

Indicates whether the floating-point hardware implementation supports exception trapping:

0x0

Not supported.

[11:8]FPDP

Indicates the hardware support for floating-point double-precision operations:

0x2

Supported, VFPv3 or greater.

See the ARM® Architecture Reference Manual, ARMv8 for more information.

[7:4]FPSP

Indicates the hardware support for floating-point single-precision operations:

0x2

Supported, VFPv3 or greater.

See the ARM® Architecture Reference Manual, ARMv8 for more information.

[3:0]SIMDReg

Indicates support for the Advanced SIMD register bank:

0x2

Supported, 32 x 64-bit registers supported.

See the ARM® Architecture Reference Manual, ARMv8 for more information.


To access the MVFR0_EL1:

MRS <Xt>, MVFR0_EL1 ; Read MVFR0_EL1 into Xt

Table 2.8 shows the register access encoding.

Table 2.8. MVFR0_EL1 access encoding

op0op1CRnCRmop2
1100000000011000

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