2.1. Accessing the feature identification registers

Software can identify the Advanced SIMD and Floating-point features using the feature identification registers in the AArch64 and AArch32 execution states.

You can access the feature identification registers in the AArch64 execution state using the MRS instructions, for example:

MRS <Xt>, ID_AA64PFR0_EL1 ; Read ID_AA64PFR0_EL1 into Xt
MRS <Xt>, MVFR0_EL1       ; Read MVFR0_EL1 into Xt
MRS <Xt>, MVFR1_EL1       ; Read MVFR1_EL1 into Xt
MRS <Xt>, MVFR2_EL1       ; Read MVFR2_EL1 into Xt

You can access the feature identification registers in the AArch32 execution state using the VMRS instructions, for example:

VMRS <Rt>, FPSID ; Read FPSID into Rt
VMRS <Rt>, MVFR0 ; Read MVFR0 into Rt
VMRS <Rt>, MVFR1 ; Read MFFR1 into Rt
VMRS <Rt>, MVFR2 ; Read MVFR2 into Rt

Table 2.1 lists the feature identification registers for the Advanced SIMD and Floating-point Extension.

Table 2.1. Advanced SIMD and Scalar Floating-point feature identification registers

AArch64 nameAArch32 nameDescription
ID_AA64PFR0_EL1-Gives additional information about implemented processor features in AArch64. See the ARM® Cortex®-A53 MPCore Processor Technical Reference Manual.
-FPSIDSee Floating-Point System ID Register.
MVFR0_EL1MVFR0

See:

MVFR1_EL1MVFR1

See:

MVFR2_EL1MVFR2

See:


Copyright © 2013-2016 ARM. All rights reserved.ARM DDI 0502G
Non-ConfidentialID041316