2.3.4. Media and Floating-point Feature Register 1

The MVFR1_EL1 characteristics are:

Purpose

Describes the features provided by the Advanced SIMD and Floating-point extensions.

Usage constraints

This register is accessible as follows:

EL0EL1(NS)EL1(S)EL2EL3 (SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

MVFR1_EL1 is architecturally mapped to AArch32 register MVFR1. See Media and Floating-point Feature Register 1.

Attributes

MVFR1_EL1 is a 32-bit register.

Figure 2.4 shows the MVFR1_EL1 bit assignments.

Figure 2.4. MVFR1_EL1 bit assignments

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Table 2.9 shows the MVFR1_EL1 bit assignments.

Table 2.9. MVFR1_EL1 bit assignments 

BitsNameFunction
[31:28]SIMDFMAC

Indicates whether the Advanced SIMD and Floating-point Extension supports fused multiply accumulate operations:

0x1

Implemented.

[27:24]FPHP

Indicates whether the Advanced SIMD and Floating-point Extension supports half-precision floating-point conversion instructions:

0x2

Instructions to convert between half-precision and single-precision, and between half-precision and double-precision, implemented.

[23:20]SIMDHP

Indicates whether the Advanced SIMD and Floating-point extension supports half-precision floating-point conversion operations:

0x1

Implemented.

[19:16]SIMDSP

Indicates whether the Advanced SIMD and Floating-point extension supports single-precision floating-point operations:

0x1

Implemented.

[15:12]SIMDInt

Indicates whether the Advanced SIMD and Floating-point extension supports integer operations:

0x1

Implemented.

[11:8]SIMDLS

Indicates whether the Advanced SIMD and Floating-point extension supports load/store instructions:

0x1

Implemented.

[7:4]FPDNaN

Indicates whether the floating-point hardware implementation supports only the Default NaN mode:

0x1

Hardware supports propagation of NaN values.

[3:0]FPFtZ

Indicates whether the floating-point hardware implementation supports only the Flush-to-Zero mode of operation:

0x1

Hardware supports full denormalized number arithmetic.


To access the MVFR1_EL1:

MRS <Xt>, MVFR1_EL1 ; Read MVFR1_EL1 into Xt

Table 2.10 shows the register access encoding.

Table 2.10. MVFR1_EL1 access encoding

op0op1CRnCRmop2
1100000000011001

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