2.5.3. Media and Floating-point Feature Register 0

The MVFR0 characteristics are:

Purpose

Describes the features provided by the Advanced SIMD and Floating-point Extension.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--ConfigROConfigConfigRO

Access to this register depends on the values of CPACR.{cp10,cp11}, NSACR.{cp10,cp11}, HCPTR.{TCP10,TCP11}, and FPEXC.EN. For details of which values of these fields allow access at which exception levels, see the ARM® Architecture Reference Manual, ARMv8.

Must be interpreted with MVFR1 and MVFR2.See Media and Floating-point Feature Register 1 and Media and Floating-point Feature Register 2.

Configurations

MVFR0 is architecturally mapped to AArch64 register MVFR0_EL1. See Media and Floating-point Feature Register 0.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

MVFR0 is a 32-bit register.

Figure 2.9 shows the MVFR0 bit assignments.

Figure 2.9. MVFR0 bit assignments

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Table 2.18 shows the MVFR0 bit assignments.

Table 2.18. MVFR0 bit assignments 

BitsNameFunction
[31:28]FPRound

Indicates the rounding modes supported by the floating-point hardware:

0x1

All rounding modes supported.

[27:24]FPShVec

Indicates the hardware support for floating-point short vectors:

0x0

Not supported.

[23:20]FPSqrt

Indicates the hardware support for floating-point square root operations:

0x1

Supported.

[19:16]FPDivide

Indicates the hardware support for floating-point divide operations:

0x1

Supported.

[15:12]FPTrap

Indicates whether the floating-point hardware implementation supports exception trapping:

0x0

Not supported.

[11:8]FPDP

Indicates the hardware support for floating-point double-precision operations:

0x2

Supported, VFPv3 or greater.

See the ARM® Architecture Reference Manual, ARMv8 for more information.

[7:4]FPSP

Indicates the hardware support for floating-point single-precision operations:

0x2

Supported, VFPv3 or greater.

See the ARM® Architecture Reference Manual, ARMv8 for more information.

[3:0]SIMDReg

Indicates support for the Advanced SIMD register bank:

0x2

Supported, 32 x 64-bit registers supported.

See the ARM® Architecture Reference Manual, ARMv8 for more information.


To access the MVFR0:

VMRS <Rt>, MVFR0 ; Read MVFR0 into Rt
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