2.3.5. Media and Floating-point Feature Register 2

The MVFR2_EL1 characteristics are:

Purpose

Describes the features provided by the Advanced SIMD and Floating-point extensions.

Usage constraints

This register is accessible as follows:

EL0EL1(NS)EL1(S)EL2EL3 (SCR.NS = 1)EL3(SCR.NS = 0)
-RORORORORO
Configurations

MVFR2_EL1 is architecturally mapped to AArch32 register MVFR2. See Media and Floating-point Feature Register 2.

Attributes

MVFR2_EL1 is a 32-bit register.

Figure 2.5 shows the MVFR2_EL1 bit assignments.

Figure 2.5. MVFR2_EL1 bit assignments

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Table 2.11 shows the MVFR2_EL1 bit assignments.

Table 2.11. MVFR2_EL1 bit assignments 

BitsNameFunction
[31:8]-

Reserved, res0.

[7:4]FPMisc

Indicates support for miscellaneous VFP features.

0x4

Supports:

  • Floating-point selection.

  • Floating-point Conversion to Integer with Directed Rounding modes.

  • Floating-point Round to Integral Floating-point.

  • Floating-point MaxNum and MinNum.

[3:0]SIMDMisc

Indicates support for miscellaneous Advanced SIMD features.

0x3

Supports:

  • Floating-point Conversion to Integer with Directed Rounding modes.

  • Floating-point Round to Integral Floating-point.

  • Floating-point MaxNum and MinNum.


To access the MVFR2_EL1:

MRS <Xt>, MVFR2_EL1 ; Read MVFR2_EL1 into Xt

Table 2.12 shows the register access encoding.

Table 2.12. MVFR2_EL1 access encoding

op0op1CRnCRmop2
1100000000011010

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