2.5.4. Media and Floating-point Feature Register 1

The MVFR1 characteristics are:

Purpose

Describes the features provided by the Advanced SIMD and Floating-point extensions.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--ConfigROConfigConfigRO

Access to this register depends on the values of CPACR.{cp10,cp11}, NSACR.{cp10,cp11}, HCPTR.{TCP10,TCP11}, and FPEXC.EN. For details of which values of these fields allow access at which exception levels, see the ARM® Architecture Reference Manual, ARMv8.

Must be interpreted with MVFR0 and MVFR2.See Media and Floating-point Feature Register 0 and Media and Floating-point Feature Register 2

Configurations

MVFR1 is architecturally mapped to AArch64 register MVFR1_EL1. See Media and Floating-point Feature Register 1.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

MVFR1 is a 32-bit register.

Figure 2.10 shows the MVFR1 bit assignments.

Figure 2.10. MVFR1 bit assignments

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Table 2.19 shows the MVFR1 bit assignments.

Table 2.19. MVFR1 bit assignments 

BitsNameFunction
[31:28]SIMDFMAC

Indicates whether the Advanced SIMD and Floating-point Extension supports fused multiply accumulate operations:

0x1

Implemented.

[27:24]FPHP

Indicates whether the Advanced SIMD and Floating-point Extension supports half-precision floating-point conversion instructions:

0x2

Instructions to convert between half-precision and single-precision, and between half-precision and double-precision, implemented.

[23:20]SIMDHP

Indicates whether the Advanced SIMD and Floating-point extension supports half-precision floating-point conversion operations:

0x1

Implemented.

[19:16]SIMDSP

Indicates whether the Advanced SIMD and Floating-point extension supports single-precision floating-point operations:

0x1

Implemented.

[15:12]SIMDInt

Indicates whether the Advanced SIMD and Floating-point extension supports integer operations:

0x1

Implemented.

[11:8]SIMDLS

Indicates whether the Advanced SIMD and Floating-point extension supports load/store instructions:

0x1

Implemented.

[7:4]FPDNaN

Indicates whether the floating-point hardware implementation supports only the Default NaN mode:

0x1

Hardware supports propagation of NaN values.

[3:0]FPFtZ

Indicates whether the floating-point hardware implementation supports only the Flush-to-Zero mode of operation:

0x1

Hardware supports full denormalized number arithmetic.


To access the MVFR1:

VMRS <Rt>, MVFR1 ; Read MVFR1 into Rt
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