2.3.6. Floating-point Exception Control Register

The FPEXC32_EL2 characteristics are:

Purpose

Provides access to the AArch32 register FPEXC from AArch64 state only. Its value has no effect on execution in AArch64 state.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

---RWRWRW
Configurations

FPEXC32_EL2 is architecturally mapped to AArch32 register FPEXC. See Floating-Point Exception Control register.

Attributes

FPEXC32_EL2 is a 32-bit register.

Figure 2.6 shows the FPEXC32_EL2 bit assignments.

Figure 2.6. FPEXC32_EL2 bit assignments

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Table 2.13 shows the FPEXC32_EL2 Register bit assignments.

Table 2.13. FPEXC32_EL2 bit assignments 

Bits

Name

Function

[31]

EX

Exception bit.

res0

The Cortex-A53 processor implementation does not generate asynchronous VFP exceptions.

[30]

EN

Enable bit. A global enable for the Advanced SIMD and VFP extensions:

0

The Advanced SIMD and VFP extensions are disabled. This is the reset value.

1

The Advanced SIMD and VFP extensions are enabled and operate normally.

This bit applies only to AArch32 execution, and only when EL1 is not AArch64.

[29:11]-Reserved, res0.
[10:8]-Reserved, res1.
[7:0]-Reserved, res0.

To access the FPEXC_EL2:

MRS <Xt>, FPEXC32_EL2 ; Read FPEXC32_EL2 into Xt
MSR FPEXC32_EL2, <Xt> ; Write Xt to FPEXC32_EL2

See also Accessing the feature identification registers.

Table 2.14 shows the register access encoding.

Table 2.14. FPEXC_EL2 access encoding

op0op1CRnCRmop2
1110001010011000

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