2.3.1. Floating-point Control Register

The FPCR characteristics are:

Purpose

Controls floating-point extension behavior.

Usage constraints

The accessibility to the FPCR by exception level is:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

RWRWRWRWRWRW
Configurations

The named fields in this register map to the equivalent fields in the AArch32 FPSCR. See Floating-Point Status and Control Register.

Attributes

FPCR is a 32-bit register.

Figure 2.1 shows the FPCR bit assignments.

Figure 2.1. FPCR bit assignments

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Table 2.3 shows the FPCR bit assignments.

Table 2.3. FPCR bit assignments 

Bits

Name

Function

[31:27]

-

Reserved, res0.

[26]

AHP

Alternative half-precision control bit. The possible values are:

0

IEEE half-precision format selected.

1

Alternative half-precision format selected.

[25]DN

Default NaN mode control bit. The possible values are:

0

NaN operands propagate through to the output of a floating-point operation.

1

Any operation involving one or more NaNs returns the Default NaN.

[24]FZ

Flush-to-zero mode control bit. The possible values are:

0

Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.

1

Flush-to-zero mode enabled.

[23:22]RMode

Rounding Mode control field. The encoding of this field is:

0b00

Round to Nearest (RN) mode.

0b01

Round towards Plus Infinity (RP) mode.

0b10

Round towards Minus Infinity (RM) mode.

0b11

Round towards Zero (RZ) mode.

[21:0]-Reserved, res0.

To access the FPCR:

MRS <Xt>, FPCR ; Read FPCR into XtMSR FPCR, <Xt> ; Write Xt to FPCR

Table 2.4 shows the register access encoding.

Table 2.4. FPCR access encoding

op0op1CRnCRmop2
1101101000100000

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