2.5.6. Floating-Point Exception Control register

The FPEXC characteristics are:

Purpose

Provides a global enable for the Advanced SIMD and Floating-point extension, and indicates how the state of this extension is recorded.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--ConfigRWConfigConfigRW

Access to this register depends on the values of CPACR.{cp10,cp11}, NSACR.{cp10,cp11}, and HCPTR.{TCP10,TCP11}. For details of which values of these fields allow access at which exception levels, see the ARM® Architecture Reference Manual, ARMv8.

Configurations

FPEXC is architecturally mapped to AArch64 register FPEXC32_EL2. See Floating-point Exception Control Register.

There is one copy of this register that is used in both Secure and Non-secure states.

Attributes

FPEXC is a 32-bit register.

Figure 2.12 shows the FPEXC bit assignments.

Figure 2.12. FPEXC bit assignments

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Table 2.21 shows the FPEXC Register bit assignments.

Table 2.21. FPEXC bit assignments 

Bits

Name

Function

[31]

EX

Exception bit. The Cortex-A53 processor implementation does not generate asynchronous VFP exceptions, therefore this bit is res0.

[30]

EN

Enable bit. A global enable for the Advanced SIMD and VFP extensions:

0

The Advanced SIMD and VFP extensions are disabled.

1

The Advanced SIMD and VFP extensions are enabled and operate normally.

The EN bit is cleared at reset.

This bit applies only to AArch32 execution, and only when EL1 is not AArch64.

[29:11]-Reserved, res0.
[10:8]-Reserved, res1.
[7:0]-Reserved, res0.

To access the FPEXC register:

VMRS <Rt>, FPEXC ; Read FPEXC into Rt

See also Accessing the feature identification registers.

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