2.3.2. Floating-point Status Register

The FPSR characteristics are:

Purpose

Provides floating-point system status information.

Usage constraints

This register is accessible as follows:

EL0

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

RWRWRWRWRWRW
Configurations

The named fields in this register map to the equivalent fields in the AArch32 FPSCR. See Floating-Point Status and Control Register.

Attributes

FPSR is a 32-bit register.

Note

AArch64 floating-point comparisons set flags in the PSTATE register instead.

Figure 2.2 shows the FPSR bit assignments.

Figure 2.2. FPSR bit assignments

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Table 2.5 shows the FPSR bit assignments.

Table 2.5. FPSR bit assignments 

Bits

Name

Function

[31]

N

Negative condition flag for AArch32 floating-point comparison operations.

[30]

Z

Zero condition flag for AArch32 floating-point comparison operations.

[29]C

Carry condition flag for AArch32 floating-point comparison operations.

[28]V

Overflow condition flag for AArch32 floating-point comparison operations.

[27]QC

Cumulative saturation bit. This bit is set to 1 to indicate that an Advanced SIMD integer operation has saturated since a 0 was last written to this bit.

[26:8]-Reserved, res0.
[7]IDC

Input Denormal cumulative exception bit. This bit is set to 1 to indicate that the Input Denormal exception has occurred since 0 was last written to this bit.

[6:5]-Reserved, res0.
[4]IXC

Inexact cumulative exception bit. This bit is set to 1 to indicate that the Inexact exception has occurred since 0 was last written to this bit.

[3]UFC

Underflow cumulative exception bit. This bit is set to 1 to indicate that the Underflow exception has occurred since 0 was last written to this bit.

[2]OFC

Overflow cumulative exception bit. This bit is set to 1 to indicate that the Overflow exception has occurred since 0 was last written to this bit.

[1]DZC

Division by Zero cumulative exception bit. This bit is set to 1 to indicate that the Division by Zero exception has occurred since 0 was last written to this bit.

[0]IOC

Invalid Operation cumulative exception bit. This bit is set to 1 to indicate that the Invalid Operation exception has occurred since 0 was last written to this bit.


To access the FPSR:

MRS <Xt>, FPSR; Read FPSR into Xt
MSR FPSR, <Xt>; Write Xt to FPSR

Table 2.6 shows the register access encoding.

Table 2.6. FPSR access encoding

op0op1CRnCRmop2
1101101000100001

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