2.5.2. Floating-Point Status and Control Register

The FPSCR characteristics are:

Purpose

Provides floating-point system status information and control.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

ConfigRWConfigRWConfigConfigRW

Access to this register depends on the values of CPACR.{cp10,cp11}, NSACR.{cp10,cp11}, HCPTR.{TCP10,TCP11} and FPEXC.EN. For details of which values of these fields allow access at which exception levels, see the ARM® Architecture Reference Manual, ARMv8.

Configurations

There is one copy of this register that is used in both Secure and Nonsecure states.

The named fields in this register map to the equivalent fields in the AArch64 FPCR and FPSR. See Floating-point Control Register and Floating-point Status Register.

Attributes

FPSCR is a 32-bit register.

Figure 2.8 shows the FPSCR bit assignments.

Figure 2.8. FPSCR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 2.17 shows the FPSCR bit assignments.

Table 2.17. FPSCR bit assignments

Bits Field Function
[31] N

Floating-point Negative condition code flag.

Set to 1 if a floating-point comparison operation produces a less than result.

[30]Z

Floating-point Zero condition code flag.

Set to 1 if a floating-point comparison operation produces an equal result.

[29] C

Floating-point Carry condition code flag.

Set to 1 if a floating-point comparison operation produces an equal, greater than, or unordered result.

[28] V

Floating-point Overflow condition code flag.

Set to 1 if a floating-point comparison operation produces an unordered result.

[27] QC

Cumulative saturation bit.

This bit is set to 1 to indicate that an Advanced SIMD integer operation has saturated after 0 was last written to this bit.

[26] AHP

Alternative Half-Precision control bit:

0

IEEE half-precision format selected.

1

Alternative half-precision format selected.

[25] DN

Default NaN mode control bit:

0

NaN operands propagate through to the output of a floating-point operation.

1

Any operation involving one or more NaNs returns the Default NaN.

The value of this bit only controls floating-point arithmetic. AArch32 Advanced SIMD arithmetic always uses the Default NaN setting, regardless of the value of the DN bit.

[24] FZ

Flush-to-zero mode control bit:

0

Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard.

1

Flush-to-zero mode enable.

The value of this bit only controls floating-point arithmetic. AArch32 Advanced SIMD arithmetic always uses the Flush-to-zero setting, regardless of the value of the FZ bit.

[23:22]RMode

Rounding Mode control field:

0b00

Round to Nearest (RN) mode.

0b01

Round towards Plus Infinity (RP) mode.

0b10

Round towards Minus Infinity (RM) mode.

0b11

Round towards Zero (RZ) mode.

The specified rounding mode is used by almost all floating-point instructions. AArch32 Advanced SIMD arithmetic always uses the Round to Nearest setting, regardless of the value of the RMode bits.

[21:20] Strideres0.
[19]-Reserved, res0.
[18:16]Lenres0.
[15:8]-

Reserved, res0.

[7]IDC

Input Denormal cumulative exception bit. This bit is set to 1 to indicate that the Input Denormal exception has occurred since 0 was last written to this bit.

[6:5]-

Reserved, res0.

[4]IXC

Inexact cumulative exception bit. This bit is set to 1 to indicate that the Inexact exception has occurred since 0 was last written to this bit.

[3]UFC

Underflow cumulative exception bit. This bit is set to 1 to indicate that the Underflow exception has occurred since 0 was last written to this bit.

[2]OFC

Overflow cumulative exception bit. This bit is set to 1 to indicate that the Overflow exception has occurred since 0 was last written to this bit.

[1]DZC

Division by Zero cumulative exception bit. This bit is set to 1 to indicate that the Division by Zero exception has occurred since 0 was last written to this bit.

[0]IOC

Invalid Operation cumulative exception bit. This bit is set to 1 to indicate that the Invalid Operation exception has occurred since 0 was last written to this bit.


To access the FPSCR:

VMRS <Rt>, FPSCR ; Read FPSCR into RtVMSR FPSCR, <Rt> ; Write Rt to FPSCR

Note

The Cortex-A53 processor implementation does not support the deprecated VFP short vector feature. Attempts to execute VFP data-processing instructions result in an Undefined Instruction exception.

Copyright © 2013-2016 ARM. All rights reserved.ARM DDI 0502G
Non-ConfidentialID041316