2.5.1. Floating-Point System ID Register

The FPSID characteristics are:

Purpose

Provides top-level information about the floating-point implementation.

Usage constraints

This register is accessible as follows:

EL0

(NS)

EL0

(S)

EL1

(NS)

EL1

(S)

EL2

EL3

(SCR.NS = 1)

EL3

(SCR.NS = 0)

--ConfigROConfigConfigRO
Configurations

Access to this register depends on the values of CPACR.{cp10,cp11}, NSACR.{cp10,cp11}, and HCPTR.{TCP10,TCP11}. For details of which field values permit access at specific exception levels, see the ARM® Architecture Reference Manual, ARMv8.

This register largely duplicates information held in the MIDR. ARM deprecates use of it.

Attributes

FPSID is a 32-bit register.

Figure 2.7 shows the FPSID bit assignments.

Figure 2.7. FPSID bit assignments

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Table 2.16 shows the FPSID bit assignments.

Table 2.16. FPSID bit assignments

BitsNameFunction
[31:24]Implementer

Indicates the implementer:

0x41

ARM Limited.

[23]SW

Software bit. This bit indicates that a system provides only software emulation of the floating-point instructions:

0

The system includes hardware support for floating-point operations.

[22:16]Subarchitecture

Subarchitecture version number:

0x03

VFPv3 architecture, or later, with no subarchitecture. The entire floating-point implementation is in hardware, and requires no software support code. The MVFR0, MVFR1 and MVFR2 registers indicate the VFP architecture version.

[15:8]Part number

Indicates the part number for the floating-point implementation:

0x40

Cortex-A53 processor.

[7:4]Variant

Indicates the variant number:

0x3

Cortex-A53 processor.

[3:0]Revision

Indicates the revision number for the floating-point implementation:

0x4

r0p4.


To access the FPSID:

VMRS <Rt>, FPSID ; Read FPSID into Rt
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