ARM® CoreTile Express A15×2 A7×3 Technical Reference Manual

Cortex®-A15_A7 MPCore (V2P-CA15_A7)


Table of Contents

Preface
About this book
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the CoreTile Express A15×2 A7×3 daughterboard
1.2. Precautions
1.2.1. Ensuring safety
1.2.2. Preventing damage
2. Hardware Description
2.1. CoreTile Express A15×2 A7×3 daughterboard architecture
2.2. Cortex-A15_A7 MPCore test chip
2.3. System interconnect signals
2.3.1. Overview of system interconnect signals
2.3.2. High-Speed Bus (HSB) to other daughterboard
2.3.3. Static Memory Bus (SMB)
2.3.4. MultiMedia Bus (MMB)
2.3.5. System Bus (SB)
2.3.6. Configuration Bus (CB)
2.4. Power-up configuration and resets
2.4.1. Configuration architecture
2.4.2. System configuration
2.4.3. Resets
2.4.4. Configuration and reset signals
2.5. Serial Configuration Controller (SCC)
2.6. Voltage control and process monitors
2.6.1. Voltage control and current, temperature, and power monitoring
2.6.2. Energy meter
2.7. Clocks
2.7.1. Overview of clocks
2.7.2. Daughterboard programmable clock generators
2.7.3. Test chip PLLs and clock divider logic
2.7.4. External clocks
2.8. Interrupts
2.8.1. Overview of interrupts
2.8.2. Interrupts
2.9. HDLCD
2.10. DDR2 memory interface
2.11. Debug
3. Programmers Model
3.1. About this programmers model
3.2. Daughterboard memory map
3.2.1. Overview of daughterboard memory map
3.2.2. Remapping memory
3.2.3. Overview of the memory map for the on-chip peripherals
3.3. Test chip SCC registers
3.3.1. Test chip SCC register overview
3.3.2. Test chip SCC register summary
3.3.3. Mask operation to define SMC chip select address ranges
3.3.4. Test chip SCC register descriptions
3.4. Programmable peripherals and interfaces
3.4.1. Cortex-A15 cluster
3.4.2. Cortex-A15 L2 cache controller
3.4.3. Cortex-A7 cluster
3.4.4. Cortex-A7 L2 cache controller
3.4.5. GIC-400 Interrupt controller
3.4.6. AXI network interconnect, NIC-301
3.4.7. HDLCD controller
3.4.8. Cache Coherent Interconnect, CCI-400
3.4.9. DDR2 memory controllers, DMC-400
3.4.10. Static memory controller, PL354
3.4.11. Direct memory access controller, DMA-330
3.4.12. Watchdog, SP805
3.4.13. System counter
3.4.14. System timer
A. Signal Descriptions
A.1. Daughterboard connectors
A.2. HDRX HSB multiplexing scheme
A.3. Header connectors
A.4. Debug and trace connectors
A.4.1. JTAG connector
A.4.2. Trace connectors
B. HDLCD controller
B.1. Introduction
B.2. HDLCD Programmers Model
B.2.1. About the HDLCD controller programmers model
B.2.2. Register summary
B.2.3. Register descriptions
C. Electrical Specifications
C.1. AC characteristics
D. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. CoreTile Express A15×2 A7×3 daughterboard layout
2.1. CoreTile Express A15×2 A7×3 daughterboard block diagram
2.2. Top-level view of the Cortex-A15_A7 MPCore test chip components
2.3. System connect example with optional LogicTile Express FPGA daughterboard
2.4. CoreTile Express A15×2 A7×3 configuration architecture with Motherboard Express, V2M-P1
2.5. CoreTile Express A15×2 A7×3 configuration architecture with custom motherboard
2.6. CoreTile Express A15×2 A7×3 daughterboard resets
2.7. CoreTile Express A15×2 A7×3 daughterboard configuration and reset timing cycle
2.8. Overview of SCC connectivity
2.9. System clocks overview
2.10. CoreTile Express A15×2 A7×3 daughterboard clocks
2.11. Structure of the test chip PLLs A15 PLL0 and A7 PLL0
2.12. Structure of the test chip PLL SYS PLL
2.13. CoreTile Express A15×2 A7×3 daughterboard interrupt overview
2.14. HDLCD graphics system interconnect
2.15. DDR2 memory interface
2.16. CoreTile Express A15×2 A7×3 CoreSight and trace
3.1. CoreTile Express A15×2 A7×3 daughterboard memory map
3.2. Cortex-A15_A7 on-chip peripheral memory map
3.3. Cortex-A15 CoreSight component memory map
3.4. Cortex-A15_A7 A15 and Cortex-A7 cluster integration layers
3.5. Test chip CFGREG0 Register bit assignments
3.6. Test chip CFGREG1 Register bit assignments
3.7. Test chip CFGREG2 Register bit assignments
3.8. Test chip CFGREG3 Register bit assignments
3.9. Test chip CFGREG4 Register bit assignments
3.10. Test chip CFGREG5 Register bit assignments
3.11. Test chip CFGREG6 Register bit assignments
3.12. Test chip CFGREG7 Register bit assignments
3.13. Test chip CFGREG8 Register bit assignments
3.14. Test chip CUSTOMER_ID Register bit assignments
3.15. Test chip CFGREG11 Register bit assignments
3.16. Test chip CFGREG12 Register bit assignments
3.17. Test chip CFGEG13, 15, 17, 19, 21, 23, and 25 Register bit assignments
3.18. Test chip CFGREG14, 16, 18, 20, 22, 24 and 26 Register bit assignments
3.19. Test chip CFGREG41 Register bit assignments
3.20. Test chip CFGREG42 Register bit assignments
3.21. Test chip CFGREG43 Register bit assignments
3.22. Test chip CFGREG44 Register bit assignments
3.23. Test chip CFGREG45 Register bit assignments
3.24. Test chip CFGREG46 Register bit assignments
3.25. Test chip CFGREG47 Register bit assignments
3.26. Test chip CFGREG48 Register bit assignments
3.27. Test chip APB_CLEAR Register bit assignments
3.28. Test chip TC_ID Register bit assignments
3.29. Test chip CPU_ID Register bit assignments
3.30. System counter CNTCR Control Register bit assignments
3.31. System counter CNTCVL Control Register bit assignments
3.32. System counter CNTCVU Control Register bit assignments
3.33. System counter PID0 Control Register bit assignments
3.34. System counter PID1 Control Register bit assignments
3.35. System counter PID2 Control Register bit assignments
3.36. System counter PID3 Control Register bit assignments
3.37. System counter COMPID0 Control Register bit assignments
3.38. System counter COMPID1 Control Register bit assignments
3.39. System counter COMPID2 Control Register bit assignments
3.40. System counter COMPID3 Control Register bit assignments
3.41. System counter CNTCVL Read Register bit assignments
3.42. System counter CNTCVU Read Register bit assignments
3.43. System counter PID0 Read Register bit assignments
3.44. System counter PID1 Read Register bit assignments
3.45. System counter PID2 Read Register bit assignments
3.46. System counter PID3 Read Register bit assignments
3.47. System counter COMPID0 Read Register bit assignments
3.48. System counter COMPID1 Read Register bit assignments
3.49. System counter COMPID2 Read Register bit assignments
3.50. System counter COMPID3 Read Register bit assignments
3.51. System timer CNTPL0ACR Register bit assignments
3.52. System timer CNTPU_CVAL Register bit assignments
3.53. System timer CNTPU_CVAL Register bit assignments
3.54. System counter CNTP_TVAL Register bit assignments
3.55. System counter CNTP_CTL Register bit assignments
3.56. System counter CNTVL_CVAL Register bit assignments
3.57. System counter CNTVU_CVAL Register bit assignments
3.58. System counter CNTV_TVAL Register bit assignments
3.59. System counter CNTV_CTL Register bit assignments
3.60. System counter PID0 Register bit assignments
3.61. System counter PID1 Register bit assignments
3.62. System counter PID2 Register bit assignments
3.63. System counter PID3 Register bit assignments
3.64. System counter COMPID0 Register bit assignments
3.65. System counter COMPID1 Register bit assignments
3.66. System counter COMPID2 Register bit assignments
3.67. System counter COMPID3 Register bit assignments
A.1. CoreTile Express A15×2 A7×3 daughterboard connectors
A.2. HSB multiplexing
A.3. JTAG connector, J6
A.4. Trace Connector, J4 and J5
B.1. Version Register bit assignments
B.2. Interrupt Raw Status Register bit assignments
B.3. Interrupt Clear Register bit assignments
B.4. Interrupt Mask Register bit assignments
B.5. Interrupt Status Register bit assignments
B.6. Frame Buffer Base Address Register bit assignments
B.7. Frame Buffer Line Length Register bit assignments
B.8. Frame Buffer Line Count Register bit assignments
B.9. Frame Buffer Line Count Register bit assignments
B.10. Bus Options Register bit assignments
B.11. Vertical Synch Width Register bit assignments
B.12. Vertical Back Porch Width Register bit assignments
B.13. Vertical Data Width Register bit assignments
B.14. Vertical Front Porch Width Register bit assignments
B.15. Horizontal Synch Width Register bit assignments
B.16. Horizontal Back Porch Width Register bit assignments
B.17. Horizontal Data Width Register bit assignments
B.18. Horizontal Front Porch Width Register bit assignments
B.19. Polarities Register bit assignments
B.20. Command Register bit assignments
B.21. Little endian byte layout
B.22. Big endian byte layout
B.23. Pixel Format Register bit assignments
B.24. Color Select Register bit assignments

List of Tables

1.
2.1. Configuration and reset signals
2.2. Internal resets controlled by SCC registers
2.3. Monitoring and setting the cluster voltages
2.4. Cluster current monitors
2.5. Cluster power monitors
2.6. Device number for monitoring the Daughterboard Configuration Controller temperature
2.7. Cluster energy monitors
2.8. Cortex-A15_A7 test chip maximum clock operating frequencies
2.9. Daughterboard OSCCLK clock sources
2.10. External clock sources
2.11. Interrupts
2.12. Test chip Trace connection addresses
3.1. Daughterboard memory map
3.2. Cortex-A15_A7 on-chip peripheral memory map
3.3. Cortex-A15_A7 on-chip peripheral memory map
3.4. CoreSight component memory map
3.5. Cortex-A15_A7 A15 and Cortex-A7 cluster integration layers
3.6. Cortex-A15_A7 A15 and A7 cluster integration layers
3.7. Test chip SCC register summary
3.8. Test chip CFGREG0 Register bit assignments
3.9. Test chip CFGREG1 Register bit assignments
3.10. Test chip CFGREG2 Register bit assignments
3.11. Test chip CFGREG3 Register bit assignments
3.12. Test chip CFGREG4 Register bit assignments
3.13. Test chip CFGREG5 Register bit assignments
3.14. Test chip CFGREG6 Register bit assignments
3.15. Test chip CFGREG7 Register bit assignments
3.16. Test chip CFGREG8 Register bit assignments
3.17. Test chip CUSTOMER_ID Register bit assignments
3.18. Test chip CFGREG11 Register bit assignments
3.19. Test chip CFGREG12 Register bit assignments
3.20. CFGREG13, 15, 17, 19, 21, 23, and 25 Register bit assignments
3.21. Test chip CFGREG14, 16, 18, 20, 22, 24 and 26 Register bit assignments
3.22. Test chip CFGREG41 Register bit assignments
3.23. Test chip CFGREG42 Register bit assignments
3.24. Test chip CFGREG43 Register bit assignments
3.25. Test chip CFGREG44 Register bit assignments
3.26. Test chip CFGREG45 Register bit assignments
3.27. Test chip CFGREG46 Register bit assignments
3.28. Test chip CFGREG47 Register bit assignments
3.29. Test chip CFGREG48 Register bit assignments
3.30. Test chip APB_CLEAR Register bit assignments
3.31. Test chip TC_ID Register bit assignments
3.32. Test chip CPUID Register bit assignments
3.33. Cortex-A15 Level-2 cache controller implementation
3.34. Cortex-A7 Level-2 cache controller implementation
3.35. Interrupt controller implementation
3.36. AXI network interconnect implementation
3.37. HDLCD controller implementation
3.38. cache controller implementation
3.39. DDR2 memory controllers implementation
3.40. Static memory controller implementation
3.41. DMA implementation
3.42. Watchdog implementation
3.43. System counter implementation
3.44. System counter control register summary
3.45. System counter CNTCR Control Register bit assignments
3.46. System counter CNTCVL Control Register bit assignments
3.47. System counter CNTCVU Control Register bit assignments
3.48. System counter CNTFID0 Control Register bit assignments
3.49. System counter PIDO Control Register bit assignments
3.50. System counter PID1 Control Register bit assignments
3.51. System counter PID2 Control Register bit assignments
3.52. System counter PID3 Control Register bit assignments
3.53. System counter COMPID0 Control Register bit assignments
3.54. System counter COMPID1 Control Register bit assignments
3.55. System counter COMPID2 Control Register bit assignments
3.56. System counter COMPID3 Control Register bit assignments
3.57. System counter read register summary
3.58. System counter CNTCVL Read Register bit assignments
3.59. System counter CNTCVU Read Register bit assignments
3.60. System counter CNTFID0 Read Register bit assignments
3.61. System counter PIDO Read Register bit assignments
3.62. System counter PID1 Read Register bit assignments
3.63. System counter PID2 Read Register bit assignments
3.64. System counter PID3 Read Register bit assignments
3.65. System counter COMPID0 Read Register bit assignments
3.66. System counter COMPID1 Read Register bit assignments
3.67. System counter COMPID2 Read Register bit assignments
3.68. System counter COMPID3 Read Register bit assignments
3.69. System timer control register summary
3.70. System timer CNTLPCT Register bit assignments
3.71. System timer CNTUPCT Register bit assignments
3.72. System timer CNTLVCT Register bit assignments
3.73. System timer CNTUVCT Register bit assignments
3.74. System timer CNTFRQ Register bit assignments
3.75. System timer CNTPL0ACR Register bit assignments
3.76. System timer CNTLOFF Register bit assignments
3.77. System timer CNTVOFF Register bit assignments
3.78. System timer CNTPL_CVAL Register bit assignments
3.79. System timer CNTPU_CVAL Register bit assignments
3.80. System counter CNTP_TVAL Register bit assignments
3.81. System counter CNTP_CTL Register bit assignments
3.82. System counter CNTVL_CVAL Register bit assignments
3.83. System counter CNTVU_CVAL Register bit assignments
3.84. System counter CNTV_TVAL Register bit assignments
3.85. System counter CNTV_CTL Register bit assignments
3.86. System counter PID0 Register bit assignments
3.87. System counter PID1 Register bit assignments
3.88. System counter PID2 Register bit assignments
3.89. System counter PID3 Register bit assignments
3.90. System counter COMPID0 Register bit assignments
3.91. System counter COMPID1 Register bit assignments
3.92. System counter COMPID2 Register bit assignments
3.93. System counter COMPID3 Register bit assignments
A.1. JTAG connector (J6) signal list
A.2. Trace Single connector, J4, signal list
A.3. Trace Dual connector, J5, signal list
B.1. Register summary
B.2. Version Register bit assignments
B.3. Raw Interrupt Register bit assignments
B.4. Interrupt Clear Register bit assignments
B.5. Interrupt Mask Register bit assignments
B.6. Interrupt Status Register bit assignments
B.7. Frame Buffer Base Address Register bit assignments
B.8. Frame Buffer Line Length Register bit assignments
B.9. Frame Buffer Line Count Register bit assignments
B.10. Frame Buffer Line Count Register bit assignments
B.11. Bus Options Register bit assignments
B.12. Vertical Synch Register bit assignments
B.13. Vertical Back Porch Register bit assignments
B.14. Vertical Data Width Register bit assignments
B.15. Vertical Front Porch Width Register bit assignments
B.16. Horizontal Synch Width Register bit assignments
B.17. Horizontal Synch Width Register bit assignments
B.18. Horizontal Data Width Register bit assignments
B.19. Horizontal Front Porch Register bit assignments
B.20. Polarities Register bit assignments
B.21. Command Register bit assignments
B.22. Pixel Format Register bit assignments
B.23. Color Select Register bit assignments
C.1. AC characteristics
D.1. Issue A
D.2. Difference between issue A and issue B
D.3. Differences between issue B and issue C
D.4. Differences between issue C and issue D
D.5. Differences between issue D and issue E
D.6. Differences between issue E and issue F
D.7. Differences between issue F and issue G
D.8. Differences between issue G and issue H
D.9. Difference between Issue H and Issue I

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

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The system should be powered down when not in use.

The daughterboard generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • Ensure attached cables do not lie across the card.

  • Reorient the receiving antenna.

  • Increase the distance between the equipment and the receiver.

  • Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

  • Consult the dealer or an experienced radio/TV technician for help.

Note

It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision AJune 2012First release for V2P-CA15_A7
Revision BJuly 2012Second release for V2P-CA15_A7
Revision C10 August 2012Third release for V2P-CA15_A7
Revision D12 October 2012Fourth release for V2P-CA15_A7
Revision E31 March 2013Fifth release for V2P-CA15_A7
Revision F28 June 2013Sixth release for V2P-CA15_A7
Revision G16 October 2013Seventh release for V2P-CA15_A7
Revision H29 May 2014Eighth release for V2P-CA15_A7
Revision I16 December 2016Ninth release for V2P-CA15_A7
Copyright © 2012-2014, 2016 ARM Limited or its affiliates. All rights reserved.ARM DDI 0503I
Non-ConfidentialID121616