ARM® CoreLink™ TZC-400 TrustZone® Address Space Controller Technical Reference Manual

Revision: r0p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Other Publications
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the TZC-400
1.1.1. TZC-400 overview
1.1.2. TZC-400 example system
1.2. Compliance
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.6. Test features
1.7. Product documentation, design flow, and architecture
1.8. Product revisions
2. Functional Description
2.1. TZC-400 interfaces
2.1.1. Clock and reset signals
2.1.2. AXI low-power interface signals
2.1.3. ACE-Lite interfaces
2.1.4. QoS Virtual Networks interface
2.1.5. APB slave interface
2.1.6. Identity input signals
2.1.7. Interrupt signal
2.1.8. Revision AND configuration signal
2.2. TZC-400 operation
2.2.1. Access filtering with regions
2.2.2. Speculative accesses
2.2.3. Fast path selection
2.2.4. Gate keeper
2.2.5. Barriers
2.2.6. Lock transaction sequences
2.2.7. Exclusive accesses
2.2.8. Access latencies
2.2.9. Denied ACE-Lite transactions
2.2.10. Reset
2.3. Constraints of use
2.3.1. Changing the programmers view on an active system
2.3.2. Clock gating
3. Programmers Model
3.1. About this programmers model
3.2. Register summary
3.3. Register descriptions
3.3.1. Build configuration register
3.3.2. Action register
3.3.3. Gate keeper register
3.3.4. Speculation control register
3.3.5. Interrupt status register
3.3.6. Interrupt clear register
3.3.7. Fail address low register
3.3.8. Fail address high register
3.3.9. Fail control register
3.3.10. Fail ID register
3.3.11. Region base address low register
3.3.12. Region base address high register
3.3.13. Region top address low register
3.3.14. Region top address high register
3.3.15. Region attributes register
3.3.16. Region ID access register
3.3.17. Peripheral ID 4 register
3.3.18. Peripheral ID 5 register
3.3.19. Peripheral ID 6 register
3.3.20. Peripheral ID 7 register
3.3.21. Peripheral ID 0 register
3.3.22. Peripheral ID 1 register
3.3.23. Peripheral ID 2 register
3.3.24. Peripheral ID 3 register
3.3.25. Component ID 0 register
3.3.26. Component ID 1 register
3.3.27. Component ID 2 register
3.3.28. Component ID 3 register
A. Signal Descriptions
A.1. Signal direction
A.2. Clock and reset signals
A.3. AXI low-power interface signals
A.4. ACE-Lite signals
A.5. QoS Virtual Network signals
A.5.1. AXI VN signals
A.6. APB signals
A.7. Identity signals
A.8. Interrupt signal
A.9. Configuration signals
B. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. TZC-400 overview
1.2. TZC-400 example system
2.1. TZC-400 interfaces
2.2. AXI low-power interface signals in the TZC-400
2.3. TZC-400 using FPIDs and NSAIDs
2.4. Region mapping example on a 32-bit address map for a filter unit
2.5. Non-secure accesses
3.1. Build configuration register bit assignment
3.2. Action register bit assignments
3.3. Gate keeper register bit assignments
3.4. Speculation control register bit assignments
3.5. Interrupt status register bit assignments
3.6. Interrupt clear register bit assignments
3.7. Fail address low register bit assignments.
3.8. Fail address high register bit assignments
3.9. Fail control register bit assignments
3.10. Fail ID register bit assignments
3.11. Region base address low register bit assignments
3.12. Region base address high register bit assignments
3.13. Region top address low register bit assignments
3.14. Region top address high register bit assignments
3.15. Region attributes register bit assignments
3.16. Region ID access register bit assignments
3.17. Peripheral ID 4 register bit assignments
3.18. Peripheral ID 0 register bit assignments
3.19. Peripheral ID 1 register bit assignments
3.20. Peripheral ID 2 register bit assignments
3.21. Peripheral ID 3 register bit assignments
3.22. Component ID 0 register bit assignments
3.23. Component ID 1 register bit assignments.
3.24. Component ID 2 register bit assignments
3.25. Component ID 3 register bit assignments
A.1. Master interface and slave interface signal direction

List of Tables

1.
1.1. Configurable parameters
2.1. ACE-Lite interface attributes
2.2. Programmable parameters of regions
2.3. Permissions for Secure accesses
2.4. Minimum access latencies
3.1. Register summary
3.2. Build configuration register bit assignments
3.3. Action register bit assignments
3.4. Gate keeper register bit assignments
3.5. Speculation control register bit assignments
3.6. Interrupt status register bit assignments
3.7. Interrupt clear register bit assignments
3.8. Fail address low register bit assignments
3.9. Fail address high register bit assignments
3.10. Fail control register bit assignments
3.11. Fail ID register bit assignments
3.12. Region base address low register bit assignments
3.13. Region base address high register bit assignments
3.14. Region top address low register bit assignments
3.15. Region top address high register bit assignments
3.16. Region attributes register bit assignments
3.17. Region ID access register bit assignments
3.18. Peripheral ID 4 register bit assignments
3.19. Peripheral ID 0 register bit assignments
3.20. Peripheral ID 1 register bit assignments
3.21. Peripheral ID 2 register bit assignments
3.22. Peripheral ID 3 register bit assignments
3.23. Component ID 0 register bit assignments
3.24. Component ID 1 register bit assignments
3.25. Component ID 2 register bit assignments
3.26. Component ID 3 register bit assignments
A.1. Clocks and resets
A.2. Low-power interface signals
A.3. ACE-Lite signals
A.4. VN signals
A.5. AXI VN signals
A.6. Control unit APB signals
A.7. Identity input signals
A.8. Interrupt signal
A.9. Static configuration signals
B.1. Issue A
B.2. Differences between issue A and issue B
B.3. Differences between issue B and issue C

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM® in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM® in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A10 May 2013First release for r0p0
Revision B15 July 2013First release for r0p1
Revision C20 February 2014Second release for r0p1
Copyright © 2013, 2014 ARM. All rights reserved.ARM DDI 0504C
Non-ConfidentialID063014