Juno ARM® Development Platform SoC Technical Reference Manual

Revision: r0p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the ARM Development Platform (ADP) SoC
1.2. Components
1.3. Compliance
1.3.1. ARM Architecture
1.3.2. Generic Interrupt Controller architecture
1.3.3. Advanced Microcontroller Bus Architecture
1.3.4. Platform Design Documents and white papers
1.3.5. big.LITTLE
1.3.6. Virtualization
1.4. Product documentation and architecture
1.5. ARM IP revisions
1.6. Product revisions
2. Functional Description
2.1. ADP components
2.2. Application processors
2.2.1. Processor affinity
2.2.2. Cortex-A57 cluster
2.2.3. Cortex-A53 cluster
2.2.4. Interrupts
2.2.5. Interconnects
2.2.6. Events
2.3. Mali-T624 Graphics Processing Unit
2.4. Memory
2.4.1. Application memory map
2.4.2. CoreLink DMC-400 Memory Controller
2.4.3. Memory bus architecture
2.4.4. TrustZone system design
2.5. Application processor peripherals
2.5.1. USB 2.0 host controller
2.5.2. Direct Memory Access (DMA) controller
2.5.3. HDLCD controller
2.5.4. Coherency support for non-ACE-Lite masters
2.5.5. Static Memory Controller (SMC), PL354
2.5.6. I2S interface
2.5.7. I2C interface
2.5.8. UART
2.5.9. System override
2.6. Interconnect and memory system
2.6.1. CoreLink NIC-400 Network Interconnect
2.6.2. CoreLink MMU-401 and MMU-400 System Memory Management (SMMU) components
2.6.3. CoreLink DMC-400 Dynamic Memory Controller
2.7. Security
2.7.1. About security
2.7.2. Trusted Base System Architecture (TBSA) compliance
2.7.3. ADP device security model
2.7.4. Trusted entropy source
2.7.5. Trusted root-key storage
2.7.6. Trusted non-volatile counters
2.7.7. Trusted HDLCD controller
2.7.8. Secure on-chip memories
2.7.9. Interconnect IP
2.8. Timers
2.8.1. Time domains
2.8.2. Counter and timer components
2.8.3. Processor power modes
2.8.4. Watchdog timers
2.9. Debug and profiling
2.9.1. ADP debug architecture
2.9.2. Cortex-A57 and Cortex-A53 processor debug architecture
2.9.3. Trace
2.9.4. Cross triggers
2.9.5. System Trace Macrocell
2.9.6. Debugger connectivity
2.9.7. CoreSight timestamps
2.10. Boot
2.10.1. About boot
2.10.2. Initial power, clock, and reset requirements for boot
2.11. HDLCD controller
2.12. PCIe
2.12.1. Configuration space
2.12.2. Interrupts
2.12.3. MSI
2.12.4. Clock requirements
2.12.5. Limitations
2.13. Thin Links
2.13.1. About Thin Links
2.13.2. TLX master and slave bridges
2.13.3. System latency
3. Programmers Model
3.1. About this programmers model
3.2. Application processor interrupt map
3.2.1. CPUID definition
3.2.2. Application processors interrupt map
3.2.3. Board interrupts
3.2.4. Message Signaled Interrupt (MSI) unit
3.2.5. System error interrupts
3.3. Application processor memory map
3.3.1. Boot region
3.3.2. SMC interface region
3.3.3. Peripherals region
3.3.4. DRAM
3.3.5. Application memory map summary
3.4. ADP System Security Control Registers
3.4.1. About the ADP programmers model
3.4.2. Register summary
3.4.3. Register descriptions
3.4.4. Message Handling Unit (MHU)
3.5. System override registers
3.5.1. Register summary
3.5.2. Register descriptions
3.6. MHU Registers
3.6.1. Register summary
3.6.2. Register descriptions
3.7. SoC Interconnect NIC-400 Registers
3.7.1. SoC Interconnect NIC-400 sub-block memory map
3.7.2. Register summary
3.8. Compute subsystem NIC-400 Registers
3.8.1. Compute subsystem NIC-400 Sub-block memory map
3.8.2. Register summary
3.9. HDLCD Registers
3.9.1. Register summary
3.9.2. Register descriptions
3.10. PCIe Control Registers
3.10.1. Register summary
3.10.2. Register descriptions
3.11. PCIe Root Port configuration registers
3.11.1. Register summary
3.11.2. Control and status Registers descriptions
3.11.3. Interrupt and event Registers descriptions
3.11.4. Address translation Registers descriptions
3.12. MSI Registers
3.12.1. Register summary
3.12.2. Register descriptions
3.13. Trusted Entropy Source Registers
3.13.1. Register summary
3.13.2. Register descriptions
A. Subcomponent Configurations
A.1. Cortex-A57 processor cluster
A.2. Cortex-A53 processor cluster
A.3. Mali-T624 GPU
A.4. CoreLink MMU-40x System Memory Management Unit (SMMU) components
A.5. CoreLink DMC-400 Dynamic Memory Controller (DMC)
A.6. CoreLink Static Memory Controller (SMC), PL354
B. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. ADP block diagram
2.1. Application processor interrupt connections
2.2. I2S integration
2.3. I2C interface pad connections
2.4. UART integration
2.5. Configuration flow chart
2.6. ISR flow chart
2.7. Trusted display controller
2.8. ADP debug architecture, excluding timestamp distribution
2.9. TLX-400 AXI interfaces
3.1. ADP top-level application memory map
3.2. ADP boot area memory map
3.3. ADP SMC interface area memory map
3.4. ADP peripherals region memory map, 0x1F00_0000-0x2F00_0000
3.5. CoreSight debug and trace region memory map
3.6. System peripherals memory map
3.7. Processor peripherals region memory map
3.8. Graphics region memory map
3.9. ADP peripherals region memory map, 0x6000_0000-0x8000_0000
3.10. DRAM memory map
3.11. SSC_DBGCFG_STAT Register bit assignments
3.12. SSC_DBGCFG_SET Register bit assignments
3.13. SSC_DBGCFG_CLR Register bit assignments
3.14. SSC_AUXDBGCFG Register bit assignments
3.15. SSC_SWDHOD Register bit assignments
3.16. SSC_GPRETN Register bit assignments
3.17. SSC_VERSION Register bit assignments
3.18. SSC_PID_4 Register bit assignments
3.19. SSC_PID_0 Register bit assignments
3.20. SSC_PID_1 Register bit assignments
3.21. SSC_PID_2 Register bit assignments
3.22. SSC_PID_3 Register bit assignments
3.23. <n>_STAT Register bit assignments
3.24. <n>_SET Register bit assignments
3.25. <n>_CLEAR Register bit assignments
3.26. MHU_SCFG Register bit assignments
3.27. MHU_PID_4 Register bit assignments
3.28. MHU_PID_1 Register bit assignments
3.29. MHU_PID_2 Register bit assignments
3.30. MHU_PID_3 Register bit assignments
3.31. MHU_PID_0 Register bit assignments
3.32. COMP_ID0 Register bit assignments
3.33. MHU COMP_ID1 Register bit assignments
3.34. MHU COMP_ID2 Register bit assignments
3.35. MHU COMP_ID3 Register bit assignments
3.36. Version Register bit assignments
3.37. Interrupt Raw Status Register bit assignments
3.38. Interrupt Clear Register bit assignments
3.39. Interrupt Mask Register bit assignments
3.40. Interrupt Status Register bit assignments
3.41. Frame Buffer Base Address Register bit assignments
3.42. Frame Buffer Line Length Register bit assignments
3.43. Frame Buffer Line Count Register bit assignments
3.44. Frame Buffer Line Count Pitch bit assignments
3.45. Bus Options Register bit assignments
3.46. Vertical Synch Width Register bit assignments
3.47. Vertical Back Porch Width Register bit assignments
3.48. Vertical Data Width Register bit assignments
3.49. Vertical Front Porch Width Register bit assignments
3.50. Horizontal Synch Width Register bit assignments
3.51. Horizontal Back Porch Width Register bit assignments
3.52. Horizontal Data Width Register bit assignments
3.53. Horizontal Front Porch Width Register bit assignments
3.54. Polarities Register bit assignments
3.55. Command Register bit assignments
3.56. Little endian byte layout
3.57. Big endian byte layout
3.58. Pixel Format Register bit assignments
3.59. Color Select Register bit assignments
3.60. PLL Config Register bit assignments
3.61. PCIe Reset Control Register bit assignments
3.62. PCIe Reset Status Register bit assignments
3.63. PCIe Clock Control Register bit assignments
3.64. Secure Register bit assignments
3.65. PID4 Register bit assignments
3.66. PID0 Register bit assignments
3.67. PID1 Register bit assignments
3.68. PID2 Register bit assignments
3.69. PID3 Register bit assignments
3.70. ID0 Register bit assignments
3.71. ID1 Register bit assignments
3.72. ID2 Register bit assignments
3.73. ID3 Register bit assignments
3.74. BRIDGE_VER Register bit assignments
3.75. BRIDGE_BUS Register bit assignments
3.76. PCIE_IF_CONF Register bit assignments
3.77. PCIE_BASIC_CONF Register bit assignments
3.78. PCIE_BASIC_STATUS Register bit assignments
3.79. PID4 Register bit assignments
3.80. PID0 Register bit assignments
3.81. PID1 Register bit assignments
3.82. PID2 Register bit assignments
3.83. PID3 Register bit assignments
3.84. ID0 Register bit assignments
3.85. ID1 Register bit assignments
3.86. ID2 Register bit assignments
3.87. ID3 Register bit assignments
3.88. Status, STATUS, Register bit assignments
3.89. Interrupt Mask, INTMASK, Register bit assignments
3.90. Control, CONTROL, Register bit assignments

List of Tables

1.
1.1. IP revisions
2.1. Application processor affinity values
2.2. Application processor peripherals
2.3. DMA-330 configuration
2.4. DMA-330 peripheral request interface mapping
2.5. Display resolutions
2.6. HDLCD controller configuration parameters
2.7. Permitted ACE-Lite write transactions
2.8. Permitted ACE-Lite read transactions
2.9. PL354 chip selects and address ranges
2.10. Minimum ic_clk frequency
2.11. Baud rates
2.12. Trusted root-key storage registers
2.13. Trusted non-volatile counters
2.14. Frames for counter and timer components
2.15. Trigger sources, sinks and their connectivity
2.16. STM views and associated STPv2 Master ID
2.17. STM hardware events inputs
2.18. Bandwidth requirements of external masters
2.19. System latency
3.1. GIC core IDs for ADP configurations
3.2. Private peripheral interrupts
3.3. Application processor cluster shared peripheral interrupt map
3.4. Board interrupts
3.5. Application memory map
3.6. System Security Control Register summary
3.7. SSC_DBGCFG_STAT Register bit assignments
3.8. SSC_DBGCFG_SET Register bit assignments
3.9. SSC_DBGCFG_CLR Register bit assignments
3.10. SSC_AUXDBGCFG Register bit assignments
3.11. SSC_SWDHOD Register bit assignments
3.12. SSC_GPRETN Register bit assignments
3.13. SSC_VERSION Register bit assignments
3.14. SSC_PID_4 Register bit assignments
3.15. SSC PID_0 Register bit assignments
3.16. SSC PID_1 Register bit assignments
3.17. SSC PID_2 Register bit assignments
3.18. SSC PID_3 Register bit assignments
3.19. SSC COMP_ID0 Register
3.20. SSC COMP_ID1 Register
3.21. SSC COMP_ID2 Register
3.22. SSC COMP_ID3 Register
3.23. System Override Registers summary
3.24. SEC_HDLCD Register
3.25. GPR_0 Register
3.26. GPR_1 Register
3.27. MHU Register summary
3.28. <n>_STAT Register bit assignments
3.29. <n>_SET Register bit assignments
3.30. <n>_CLEAR Register bit assignments
3.31. MHU_SCFG register bit assignments
3.32. MHU PID_4 register
3.33. MHU PID_1 register bit assignments
3.34. MHU PID_2 register bit assignments
3.35. MHU PID_3 register bit assignments
3.36. MHU PID_0 register bit assignments
3.37. MHU COMP_ID0 register bit assignments
3.38. MHU COMP_ID1 Register bit assignments
3.39. MHU COMP_ID2 Register bit assignments
3.40. MHU COMP_ID3 Register bit assignments
3.41. SoC Interconnect NIC-400 sub-block memory map
3.42. Address Region Control Registers
3.43. ID Registers
3.44. USB_EHCI sub-block registers
3.45. TLX_MST sub-block registers
3.46. USB_OHCI sub-block registers
3.47. PL354_SMC sub-block registers
3.48. APB4_BRIDGE sub-block registers
3.49. BOOTSEC_BRIDGE sub-block registers
3.50. SECURE_BRIDGE sub-block registers
3.51. CSS_SC sub-block registers
3.52. CSS_M sub-block registers
3.53. HDLCD_0 sub-block registers
3.54. HDLCD_1 sub-block registers
3.55. DMA330_DMA sub-block registers
3.56. TLX_SLV sub-block registers
3.57. USB_MST sub-block registers
3.58. IB0 sub-block registers
3.59. Compute subsystem NIC-400 sub-block memory map
3.60. Address Region Control Registers
3.61. ID Registers
3.62. CCISLAVE sub-block registers
3.63. CUST_EXT_SLV sub-block registers
3.64. SCP sub-block registers
3.65. CS_DAP sub-block registers
3.66. CS_ETR sub-block registers
3.67. Register summary
3.68. Version Register bit assignments
3.69. Interrupt Raw Status Register bit assignments
3.70. Interrupt Clear Register bit assignments
3.71. Interrupt Mask Register bit assignments
3.72. Interrupt Status Register bit assignments
3.73. Frame Buffer Base Address Register bit assignments
3.74. Frame Buffer Line Length Register bit assignments
3.75. Frame Buffer Line Count Register bit assignments
3.76. Frame Buffer Line Pitch Register bit assignments
3.77. Bus Options Register bit assignments
3.78. Vertical Synch Register bit assignments
3.79. Vertical Back Porch Register bit assignments
3.80. Vertical Data Width Register bit assignments
3.81. Vertical Front Porch Width Register bit assignments
3.82. Horizontal Synch Width Register bit assignments
3.83. Horizontal Back Porch Register bit assignments
3.84. Horizontal Data Width Register bit assignments
3.85. Horizontal Front Porch Register bit assignments
3.86. Polarities Register bit assignments
3.87. Command Register bit assignments
3.88. Pixel Format Register bit assignments
3.89. Color Select Register bit assignments
3.90. PCIe control Registers summary
3.91. PLL Config Register bit assignments
3.92. PCIe Reset Control Register bit assignments
3.93. Valid combinations of RC_REL and PHY_REL
3.94. PCIe Reset Status Register bit assignments
3.95. PCIe Clock Control Register bit assignments
3.96. Secure Register bit assignments
3.97. PID4 Register bit assignments
3.98. PID0 Register bit assignments
3.99. PID1 Register bit assignments
3.100. PID2 Register bit assignments
3.101. PID3 Register bit assignments
3.102. ID0 Register bit assignments
3.103. ID1 Register bit assignments
3.104. ID2 Register bit assignments
3.105. ID3 Register bit assignments
3.106. PCIe Root Port configuration Registers summary
3.107. BRIDGE_VER Register bit assignments
3.108. BRIDGE_BUS Register bit assignments
3.109. PCIE_IF_CONF Register bit assignments
3.110. PCIE_BASIC_CONF Register bit assignments
3.111. PCIE_BASIC_STATUS Register bit assignments
3.112. PCIE_VC_CRED_0 Register bit assignments
3.113. PCIE_VC_CRED_1 Register bit assignments
3.114. PCIE_PCI_IDS_0 Register bit assignments
3.115. PCIE_PCI_IDS_1 Register bit assignments
3.116. PCIE_PCI_IDS_2 Register bit assignments
3.117. PCIE_PCI_LPM Register bit assignments
3.118. PCIE_PCI_IRQ _0 Register bit assignments
3.119. PCIE_PCI_IRQ_1 Register bit assignments
3.120. PCIE_PCI_IRQ_2 Register bit assignments
3.121. PCIE_PEX_DEV Register bit assignments
3.122. PCIE_PEX_LINK Register bit assignments
3.123. PCIE_PEX_SPC Register bit assignments
3.124. PCIE_PEX_SPC2 Register bit assignments
3.125. PCIE_PEX_NFTS Register bit assignments
3.126. PCIE_BAR_WIN Register bit assignments
3.127. PCIE_EQ_PRESET_LANE_0_1 Register bit assignments
3.128. PCIE_EQ_PRESET_LANE_2_3 register bit assignments
3.129. PCIE_CFGNUM Register bit assignments
3.130. PM_CONF_0 Register bit assignments
3.131. PM_CONF_1 Register bit assignments
3.132. PM_CONF_2 Register bit assignments
3.133. ISTATUS_LOCAL Register bit assignments
3.134. ICMD_PM Register bit assignments
3.135. ISTATUS_PM Register bit assignments
3.136. ISTATUS_P_ADT_WIN0 Register bit assignments
3.137. ISTATUS_P_ADT_WIN0 Register nibble form
3.138. ISTATUS_P_ADT_WIN1 Register bit assignments
3.139. ISTATUS_P_ADT_WIN1 Register nibble form
3.140. ISTATUS_A_ADT_SLV0 Register bit assignments
3.141. ISTATUS_A_ADT_SLV0 Register nibble form
3.142. Address translation table register blocks
3.143. Address translation table Registers
3.144. SRC_ADDR_LO Register bit assignments
3.145. SRC_ADDR_UP Register bit assignments
3.146. TRSL_ADDR_LO Register bit assignments
3.147. TRSL_ADDR[63:32] Register bit assignments
3.148. TRSL_PARAM Register bit assignments
3.149. MSI Registers summary
3.150. MSI_TYPER Register bit assignments
3.151. MSI_IIDR Register bit assignments
3.152. PID4 Register bit assignments
3.153. PID0 Register bit assignments
3.154. PID1 Register bit assignments
3.155. PID2 Register bit assignments
3.156. PID3 Register bit assignments
3.157. ID0 Register bit assignments
3.158. ID1 Register bit assignments
3.159. ID2 Register bit assignments
3.160. ID3 Register bit assignments
3.161. Trusted Entropy Source Registers summary
3.162. RNG Output Register (OUTPUT_0)
3.163. RNG Output, OUTPUT_1, Register bit assignments
3.164. RNG Output, OUTPUT_2, Register bit assignments
3.165. RNG Output, OUTPUT_3, Register bit assignments
3.166. Status, STATUS, Register bit assignments
3.167. Interrupt Mask, INTMASK, Register bit assignments
3.168. Configuration, CONFIG, Register bit assignments
3.169. Control, CONTROL, Register bit assignments
A.1. Cortex-A57 cluster configuration options
A.2. Cortex-A53 cluster configuration options
A.3. Mali-T624 GPU configuration options
A.4. MMU-40x configuration options
A.5. DMC-400 configuration options for DDR3-1600
A.6. PL354 configuration
B.1. Issue A
B.2. Differences between issue A and issue B

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A03 June 2014First release for r0p0
Revision B23 September 2014Second release for r0p0
Copyright © 2014. All rights reserved.ARM DDI 0515B
Non-ConfidentialID092514