A.9. MBIST interface signals

Table A.9 shows MBIST interface signals.

Table A.9. MBIST interface signals

Port NameTypeSource/destinationDescription
mbistackOutputMBIST controller

MBIST Mode Ready.

GIC-500 acknowledges that it is ready for MBIST testing.

mbistreqInput

MBIST Mode Request.

Request to GIC-500 to enable MBIST testing. This signal must be tied LOW during functional operation.

mbistresetnInput

Resets MBIST logic.

Resets functional logic to enable MBIST operation by an Active-LOW signal. This signal must be tied HIGH during functional operation.

mbistaddr[variable][a]Input

Logical address.

The width is based on the RAM with the largest number of words. You must drive the most significant bits to zero when accessing RAMs with fewer address bits.

mbistindata[variable][a]Input

Data in.

Write data. Width based on the RAM with the largest number of data bits.

mbistoutdata[variable][a]Output

Data out.

Read data. Width based on the RAM with the largest number of data bits.

mbistwriteenInput

Write control (mbistwriteen) and Read control (mbistreaden)

No access occurs if both enables are off. It is illegal to activate both enables simultaneously.

mbistreadenInput
mbistarray[1:0]Input

Array selector.

This controls which RAM array is accessed. For the single RAM configuration, this port is unused.

mbistcfgInput

MBIST ALL enable.

When enabled, allows simultaneous access to all RAM arrays for maximum array power consumption.

[a] The variable is configuration dependent.


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