3.6. Redistributor registers for control and physical LPIs summary

In GICv3 and GICv4, these registers start from RD_base and the offset of each register is defined in Table 3.7.

Offsets that are not shown are Reserved and RAZ/WI.

Table 3.7. Redistributor register summary

Offset

Name[a]

Type

Reset

Description[b]

0x0000

GICR_CTLR

RW

0x00000000

Redistributor Control Register.

0x0004

GICR_IIDR

RO

0x0000043B

Redistributor ID Register.

0x0008-0x000C

GICR_TYPER

RO

Configuration dependent[c]

Redistributor Type Register, 64-bit.

0x0010

-

-

-

Reserved.

0x0014

GICR_WAKER

RW

0x00000006

Power Management Control Register.

0x0018-0x006C

-

-

-

Reserved.

0x0070-0x0074

GICR_PROPBASER[d]

RW

0x0000000000000000Common LPI configuration table base register, 64-bit.

0x0078-0x007C

GICR_PENDBASER[d][e]RW0x0000000000000000LPI pending table base register, 64-bit.

0x0080-0xFFCC

-

-

-

Reserved.

0xFFD0

GICR_PIDR4

RO

0x00000044

Peripheral ID 4 Register.

0xFFD4

GICR_PIDR5

RO

0x00000000

Peripheral ID 5 Register.

0xFFD8

GICR_PIDR6

RO

0x00000000

Peripheral ID 6 Register.

0xFFDC

GICR_PIDR7

RO

0x00000000

Peripheral ID 7 Register.

0xFFE0

GICR_PIDR0

RO

0x00000093

Peripheral ID 0 Register.

0xFFE4

GICR_PIDR1

RO

0x000000B4

Peripheral ID 1 Register.

0xFFE8

GICR_PIDR2

RO

0x0000003B

Peripheral ID2 Register.

0xFFEC

GICR_PIDR3

RO

0x00000000

Peripheral ID 3 Register.

0xFFF0

GICR_CIDR0

RO

0x0000000D

Component ID 0 Register.

0xFFF4

GICR_CIDR1

RO

0x000000F0

Component ID 1 Register.

0xFFF8

GICR_CIDR2

RO

0x00000005

Component ID 2 Register.

0xFFFC

GICR_CIDR3

RO

0x000000B1

Component ID 3 Register.

[a] n corresponds to the number of a CPU interface.

[b] For the description of the registers that are not specific to the GIC-500, see the ARM® Generic Interrupt Controller Architecture Specification version 3.0.

[c] The reset value depends on the configuration of the GIC-500. The values of the configuration dependent fields of the GICR_TYPER are:

A3, bits[63:56] - 0.

A2, bits[55:48] - 0.

A1, bits[47:40] - the Affinity Level 1 value for this Redistributor.

A0, bits[39:32] - the Affinity Level 0 value for this Redistributor.

Processor Number, bits [23:8] - the linear Processor Number for this Redistributor.

DPGS, bit[5] - 0

Last, bit[4] - this bit is only set to one for the last Redistributor in the memory-map of the configured GIC-500.

Distributed, bit[3] - 0.

VLPIS, bit[1] - 0.

PLPIS, bit[0] - ITS and LPI support included.

[d] The existence of this register depends on the configuration of the GIC-500. If ITS and LPI support is not included, this register does not exist.

[e] ARM recommends that if possible, you set the GICR_PENDBASER Pending Table Zero bit to one. This reduces the power and time taken during initialization.


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