3.9. ITS control register summary

Table 3.10 shows the address map of the ITS control registers.

Offsets that are not shown are Reserved and RAZ/WI.

Note

This page does not exist in configurations of the GIC-500 without LPI and ITS support.

Table 3.10. ITS control register summary

Offset

Name[a]

Type

Reset

Description[b]

0x0000

GITS_CTLR

RW

0x80000000

ITS Control Register

0x0004

GITS_IIDR

RO

0x0000043B

ITS Identification Register

0x0008-0x000C

GITS_TYPER

RO

Configuration dependent[c]

ITS Type Register, 64-bit

0x0010-0x007C

---Reserved

0x0080-0x0084

GITS_CBASER

RW

0x0000000000000000

The command queue control register, 64-bit

0x0088-0x008C

GITS_CWRITER

RW

0x0000000000000000

The command queue write pointer, 64-bit

0x0090-0x0094

GITS_CREADR

RO

0x0000000000000000

The command queue read pointer, 64-bit

0x0098-0x00FC

-

-

-

Reserved

0x0100-0x0104

GITS_BASER0

RW

0x0107000000000000ITS table control register, 64-bit
0x0108-0xBFFC---Reserved

0xC000

GITS_TRKCTLRWO-Tracking Control Register

0xC004

GITS_TRKRRO0x00000000Tracking Status Register
0xC008GITS_TRKDIDRRO0x00000000Debug Tracked DID Register
0xC00CGITS_TRKPIDRRO0x00000000Debug Tracked PID Register
0xC010GITS_TRKVIDRRO0x00000000Debug Tracked ID Register
0xC014GITS_TRKTGTRRO0x00000000Debug Tracked Target Register
0xC018 GITS_TRKICRRO0x00000000Debug ITE Cache Statistics
0xC01CGITS_TRKLCRRO0x00000000Debug LPI Cache Statistics
0xC020-0xFFCC---Reserved

0xFFD0

GITS_PIDR4

RO

0x00000044

Peripheral ID 4 Register

0xFFD4

GITS_PIDR5

RO

0x00000000

Peripheral ID 5 Register

0xFFD8

GITS_PIDR6

RO

0x00000000

Peripheral ID 6 Register

0xFFDC

GITS_PIDR7

RO

0x00000000

Peripheral ID 7 Register

0xFFE0

GITS_PIDR0

RO

0x00000094

Peripheral ID 0 Register

0xFFE4

GITS_PIDR1

RO

0x000000B4

Peripheral ID 1 Register

0xFFE8

GITS_PIDR2

RO

0x0000003B

Peripheral ID2 Register

0xFFEC

GITS_PIDR3

RO

0x00000000

Peripheral ID 3 Register

0xFFF0

GITS_CIDR0

RO

0x0000000D

Component ID 0 Register

0xFFF4

GITS_CIDR1

RO

0x000000F0

Component ID 1 Register

0xFFF8

GITS_CIDR2

RO

0x00000005

Component ID 2 Register

0xFFFC

GITS_CIDR3

RO

0x000000B1

Component ID 3 Register

[a] n corresponds to the number of a CPU interface.

[b] For the description of the registers that are not specific to the GIC-500, see the ARM® Generic Interrupt Controller Architecture Specification version 3.0.

[c] The reset value depends on the configuration of the GIC-500. See the ARM® Generic Interrupt Controller Architecture Specification version 3.0 GITS_TYPER, ITS Type register for more information on the acronyms. The values of the configuration dependent fields of the GITS_TYPER register are:

HCC, bits[31:24] - the number of cores in the system, plus one.

PTA, bit[19] - 0.

SEIS, bit[18] - 0.

Devbits, bits[17:13] - ITS Device ID width, minus one.

IDbits, bits[12:8] - 0b01111.

ITT Entry size, bits[7:4] - 0b0111.

Distributed, bit[3] - 0.

Virtual, bit[1] - 0.

Physical, bit[0] - 1.


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