### 1.1.1. Topologies and terminology

Figure 1.2 shows a diagrammatic representation of the Redistributor hierarchy.

Figure 1.2. Redistributor hierarchy

### Note

The linear representation indicates the order of the cores, that is sorted by the affinity values. For example 0.0.1.1 is given the value of 3 because it is the fourth lowest affinity value in the system.

The ARM architecture defines a register in a core that identifies the logical address of the core in the system. This register, known as the Multiprocessor Affinity Register (MPIDR), has a hierarchical format. Each level of the hierarchy is known as an affinity level, with the highest affinity levels specified first:

• For an ARMv7 processor, the MPIDR defines three levels of affinity, with an implicit affinity level 3 value of 0.

• For an ARMv8 processor, the MPIDR defines four levels of affinity.

This means the affinity can be specified, using a four-field dot-decimal notation, as <Aff3>.<Aff2>.<Aff1>.<Aff0>, where Aff`n `is a value for affinity level `n`.

For most processors, for example the Cortex-A57 MPCore processor, the processor is made up from a cluster of cores that have a common affinity level 1. Each core must have a different MPIDR value, so the cores have different affinity level 0 values, beginning from 0. For example, a processor with four cores might have MPIDR values in the range 0.0.0.0-0.0.0.3. If there were two processors then the second processor might have values in the range 0.0.1.0-0.0.1.3. Typically the processor number is affinity level 1 and the core number is affinity level 0.

The GIC-500 only supports topologies where affinity levels 2 and above are the same. That is, all cores must have MPIDR values of the form 0.0.`c`.`d`, where `c` and `d` are variables. The range for `c` is assumed to start at 0 and be contiguous. The range for `d` is also assumed to start at 0 and be contiguous for each `c`. For example, the first processor must have IDs 0.0.0.0 to 0.0.0.x and the second processor must have IDs 0.0.1.0 to 0.0.1.`y`.

The GIC-500 supports up to 128 cores in up to 32 processors with a limit of eight cores per processor, and has a pair of AXI4-Stream interfaces for each processor.

When using backwards compatibility mode, GIC-500 supports the first eight cores. That is, it supports the eight cores with the lowest MPIDR values, whether they are in the same processor or not.

GIC-500 provides a Redistributor for each core, each with a corresponding set of registers. Many registers in the GIC-500 use the MPIDR value to specify cores. However, programming the Interrupt Translation Service and integrating the AXI4 slave port require an alternative linear representation. This representation is based on numbering the cores in order of increasing affinity level, starting at 0. For example, in backwards compatibility mode, GIC-500 supports cores 0-7 in linear representation.