3.5. Distributor registers for message-based SPIs summary

Table 3.6 lists the message-based SPI registers.

Table 3.6. Distributor registers for message-based SPI register summary

Offset

Name

Type

Reset

Description[a]

0x0000-0x003C---Reserved

0x0040

GICD_SETSPI_NSR

WO

-

Aliased Non-secure SPI Set Register

0x0044

-

-

-

Reserved

0x0048

GICD_CLRSPI_NSR

WO

-

Aliased Non-secure SPI Clear Register

0x004C

-

-

-

Reserved

0x0050

GICD_SETSPI_SR[b]

WO

-

Aliased Secure SPI Set Register[c]

0x0054

-

-

-

Reserved

0x0058

GICD_CLRSPI_SR[b]

WO

-

Aliased Secure SPI Clear Register[c]
0x005C-0xFFFC---Reserved

[a] For the description of the registers that are not specific to the GIC-500, see the ARM® Generic Interrupt Controller Architecture Specification version 3.0.

[b] The existence of this register depends on the configuration of the GIC-500. If Security Support is not included, this register does not exist.

[c] This register is only accessible from a Secure access.


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