3.14.1. Tracking Control Register

The GITS_TRKCTLR characteristics are:


Use this register to control LPI related debug and performance measurement features for the GIC-500.

Usage constraints

There are no usage constraints.


Present in configurations of the GIC-500 with ITS and LPI support.


See the register summary in Table 3.21.

Figure 3.11 shows the bit assignments.

Figure 3.11. GITS_TRKCTLR bit assignments

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Table 3.22 shows the bit assignments.

Table 3.22. GITS_TRKCTRL bit assignments








LPI track

Write 0b1 to capture information about the next interrupt that the ITS generated, or failed to generate because of misprogramming.

This information can then be inspected using the other registers in this page. Before using this bit, you must:

  • Enable GITS_CTLR.

  • Program GITS_BASER0 and GITS_CBASER to be valid.

  • Program GICR_WAKER to not have Sleep set.

  • Ensure that GICR_WAKER is also not Quiescent.


This register also captures certain ITS commands. Therefore ARM recommends that it is only used when the ITS command queue is empty.


Cache count reset

Write 0b1 to reset the cache hit and miss counters in GITS_TRKICR and GITS_TRKLCR.

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