3.14.7. Debug ITE Cache Statistics

The GITS_TRKICR characteristics are:


This register gives the count of hits and misses in the ITE cache since the last time the Cache Count Reset bit in the GITS_TRKCTLR register was set to 0b1.

Use this register to decide whether you want the ITE cache to be any larger. If the ratio of hits to misses is low, you can increase the size of the ITE cache to reduce latency and power consumption. The ITE cache has the same number of entries as the LPI cache, so you can increase its size using the LPI cache entries parameter. See Configurable options.

Usage constraints

There are no usage constraints.


Present in configurations of the GIC-500 with ITS and LPI support.


See the register summary in Table 3.21.

Figure 3.17 shows the bit assignments.

Figure 3.17. GITS_TRKICR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 3.28 shows the bit assignments.

Table 3.28. GITS_TRKICR bit assignments





ITE cache hits

Records the number of hits in the ITE cache
[15:0]ITE cache missesRecords the number of misses in the ITE cache

Copyright © 2014 ARM. All rights reserved.ARM DDI 0516B