3.13. Implementation defined test registers in the GICR page for PPIs and SGIs

Table 3.18 shows the address map for the implementation defined test registers in the GICR page for PPIs and SGIs.

Offsets that are not shown are Reserved and RAZ/WI.

Table 3.18. Implementation defined test register summary

Offset

Name

Type

Reset

Description

0xC000

GICR_MISCSTATUSR

RO

-

Miscellaneous Status Register

0xC080

GICR_PPISR

RO

-

Private Peripheral Interrupt Status Register

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