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Home > Programmers Model > Implementation defined test registers in the GICR page for PPIs and SGIs > Miscellaneous Status Register |
The GICR_MISCSTATUSR characteristics are:
Use this register to test the integration of the cpu_active input signals and to debug the CPU interface enables as seen by the GIC-500.
There are no usage constraints.
Always present in the GIC-500.
See the register summary in Table 3.18.
Figure 3.9 shows the bit assignments.
Table 3.19 shows the bit assignments.
Table 3.19. GICR_MISCSTATUSR bit assignments
Bits | Name | Description |
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[31][a] | CPU active state | This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read. That is, this field is one when the corresponding cpu_active input is HIGH. |
[30:3] | - | Reserved. |
[2][b] | EnableGrp1 Secure | In systems with two security states enabled, that is, when GICD_CTLR.DS is set to zero:
In systems with only a single security state enabled, that is, when GICD_CTLR.DS is set to one:
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[1][b] | EnableGrp1 Non-secure | In systems with two security states enabled, that is, when GICD_CTLR.DS is set to zero:
In systems with only a single security state enabled, that is, when GICD_CTLR.DS is set to one:
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[0][b] | EnableGrp0 | In systems with two security states enabled, that is, when GICD_CTLR.DS is set to zero:
In systems with only a single security state enabled, that is, when GICD_CTLR.DS is set to one:
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[a] This bit is undefined when ProcessorSleep or ChildrenAsleep is set for a core, because the core is presumed to be powered down. [b] These bits are a copy of the CPU interface group enables for the core corresponding to this Redistributor. These copies are undefined when ProcessorSleep or ChildrenSleep is set for a core, because the core is presumed to be powered down. These copies, which are maintained by Upstream Write packets, can become de-synchronized after an incorrect powerdown sequence. This debug register enables you to debug this scenario. For more information see the ARM® Generic Interrupt Controller Architecture Specification version 3.0. |