ARM CoreLink GIC-500 Generic Interrupt Controller Technical Reference ManualRevision: r0p0
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3.13.1. Miscellaneous Status Register

The GICR_MISCSTATUSR characteristics are:

Purpose

Use this register to test the integration of the cpu_active input signals and to debug the CPU interface enables as seen by the GIC-500.

Usage constraints

There are no usage constraints.

Configurations

Always present in the GIC-500.

Attributes

See the register summary in Table 3.18.

Figure 3.9 shows the bit assignments.

Figure 3.9. GICR_MISCSTATUSR bit assignments

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Table 3.19 shows the bit assignments.

Table 3.19. GICR_MISCSTATUSR bit assignments

Bits

Name

Description

[31][a]

CPU active state

This bit returns the actual status of the cpu_active signal for the core corresponding to the Redistributor whose register is being read. That is, this field is one when the corresponding cpu_active input is HIGH.

[30:3]

-

Reserved.

[2][b]EnableGrp1 Secure

In systems with two security states enabled, that is, when GICD_CTLR.DS is set to zero:

  • For Secure reads, returns the Group 1 Secure CPU interface enable.

  • For Non-secure reads, returns zero.

In systems with only a single security state enabled, that is, when GICD_CTLR.DS is set to one:

  • Returns zero.

[1][b]EnableGrp1 Non-secure

In systems with two security states enabled, that is, when GICD_CTLR.DS is set to zero:

  • For Secure reads, returns the Group 1 Non-secure CPU interface enable.

  • For Non-secure reads when GICD_CTLR.ARE_NS is one, returns the Group 1 Non-secure CPU interface enable.

  • For Non-secure reads when GICD_CTLR.ARE_NS is zero, returns zero.

In systems with only a single security state enabled, that is, when GICD_CTLR.DS is set to one:

  • Returns the Group 1 CPU interface enable.

[0][b]EnableGrp0

In systems with two security states enabled, that is, when GICD_CTLR.DS is set to zero:

  • For Secure reads, returns the Group 0 CPU interface enable.

  • For Non-secure reads when GICD_CTLR.ARE_NS is zero, returns the Group 1 Non-secure CPU interface enable.

  • For Non-secure reads when GICD_CTLR.ARE_NS is one, returns zero.

In systems with only a single security state enabled, that is, when GICD_CTLR.DS is set to one:

  • Returns the Group 0 CPU interface enable.

[a] This bit is undefined when ProcessorSleep or ChildrenAsleep is set for a core, because the core is presumed to be powered down.

[b] These bits are a copy of the CPU interface group enables for the core corresponding to this Redistributor. These copies are undefined when ProcessorSleep or ChildrenSleep is set for a core, because the core is presumed to be powered down. These copies, which are maintained by Upstream Write packets, can become de-synchronized after an incorrect powerdown sequence. This debug register enables you to debug this scenario. For more information see the ARM® Generic Interrupt Controller Architecture Specification version 3.0.


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