3.12.1. Extended Status Register

The GICD_ESTATUSR characteristics are:


This register guarantees that interrupt reprogramming is complete. Use this register to support legacy software that requires this guarantee so that it works with the GIC-500.

Usage constraints

There are no usage constraints.


Always present in the GIC-500.


See the register summary in Table 3.14.

Figure 3.6 shows the bit assignments.

Figure 3.6. GICD_ESTATUSR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 3.15 shows the bit assignments.

Table 3.15. GICD_ESTATUSR bit assignments






Super Register Write Pending.

This bit denotes whether any update that changes the state of any interrupt has taken effect. If the change has not taken effect the bit reads as 0b1, else the bit reads as 0b0.

You can use this bit to provide guarantees required by legacy software. See Backwards compatibility for more information.

This bit reads as 0b1 until any updates to the following interrupt attributes are guaranteed to be observed by all cores:

  • Distributor group enable.

  • Interrupt enable.

  • Group.

  • Priority.

  • Targets.




Copyright © 2014 ARM. All rights reserved.ARM DDI 0516B