3.12.1. Extended Status Register

The GICD_ESTATUSR characteristics are:

Purpose

This register guarantees that interrupt reprogramming is complete. Use this register to support legacy software that requires this guarantee so that it works with the GIC-500.

Usage constraints

There are no usage constraints.

Configurations

Always present in the GIC-500.

Attributes

See the register summary in Table 3.14.

Figure 3.6 shows the bit assignments.

Figure 3.6. GICD_ESTATUSR bit assignments

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Table 3.15 shows the bit assignments.

Table 3.15. GICD_ESTATUSR bit assignments

Bits

Name

Description

[31]

SRWP

Super Register Write Pending.

This bit denotes whether any update that changes the state of any interrupt has taken effect. If the change has not taken effect the bit reads as 0b1, else the bit reads as 0b0.

You can use this bit to provide guarantees required by legacy software. See Backwards compatibility for more information.

This bit reads as 0b1 until any updates to the following interrupt attributes are guaranteed to be observed by all cores:

  • Distributor group enable.

  • Interrupt enable.

  • Group.

  • Priority.

  • Targets.

[30:0]

-

Reserved.


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