3.12.3. Shared Peripheral Interrupt Status Register

The GICD_SPISRn characteristics are:


Enables a core to access the status of the SPI wire inputs on the Distributor.


In systems with two security states, Non-secure accesses can only read the status of Non-secure Group 1 interrupts.

Usage constraints

The Distributor provides up to 30 registers to support 960 SPIs. If you configure the GIC-500 to use fewer than 960 SPIs, it reduces the number of registers accordingly. For locations where interrupts are not implemented, the register is RAZ/WI.


Always present in the GIC-500.


See the register summary in Table 3.14.

Figure 3.8 shows the bit assignments.

Figure 3.8. GICD_SPISRn bit assignments

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Table 3.17 shows the bit assignments.

Table 3.17. GICD_SPISRn bit assignments






Returns the status of the spis inputs on the Distributor. For each bit:


spis is LOW.


spis is HIGH.


  • The spis that a bit refers to depends on its bit position and the base address offset of the Shared Peripheral Interrupt Status Registers, GICD_SPISRn.

  • These bits return the actual status of the spis input signals. The Interrupt Set-Pending Register, GICD_ISPENDRn and Interrupt Clear-Pending Register, GICD_ICPENDRn, can also provide the spis status but because you can write to these registers, they might not contain the actual status of the spis signals.

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