3.14.6. Debug Tracked Target Register

The GITS_TRKTGTR characteristics are:


This register returns the target core of the LPI that is tracked as a result of the LPI track bit in the GITS_TRKCTLR register being set to 0b1.

Usage constraints

This register is only valid when the LPI tracked field in GITS_TRKR is 1 and none of the other bits in the register is 1.


Present in configurations of the GIC-500 with ITS and LPI support.


See the register summary in Table 3.21.

Figure 3.16 shows the bit assignments.

Figure 3.16. GITS_TRKTGTR bit assignments

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Table 3.27 shows the bit assignments.

Table 3.27. GITS_TRKTGTR bit assignments







[6:0]Target core of the LPI

The target core for an interrupt that was tracked and generated an LPI successfully. This is given using the linerar representation described in Topologies and terminology. The linear representation also corresponds to the Processor Number field in the GICR_TYPER of the target core.

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