ARM CoreLink GIC-500 Generic Interrupt Controller Technical Reference Manual: 3.2. The GIC-500 register map

3.2. The GIC-500 register map

All of the GIC-500 registers have names that provide a short mnemonic for the function of the register. In these names:

The first letters indicate the logical block that the register belongs to:
- GICD indicates a Distributor register.
- GICR indicates a Redistributor register.
- GITS indicates an Interrupt Translation Service register.
The remaining letters are a mnemonic for the register, for example the GIC Distributor Control Register is called GICD_CTLR.

All pages are 64KB in size to allow for best compatibility with ARMv8. The address map within all pages is defined by the architecture specification. See the ARM^® Generic Interrupt Controller Architecture Specification version 3.0.

The number of bits of address used by the GIC-500 address map is:

18 + max(1, ceil(log₂ (total_number_of_cpus)))

Note

The write address bus might be larger than the result of this equation in certain cases. In these cases the most significant bit (MSB) referred to here might not be the MSB of the write address bus. See Effect of Device ID multiplexing for more information.

The top bit of the address selects between two sets of pages. When the MSB is LOW, the set of pages is as shown in Table 3.1:

Table 3.1. Lower half of address map

Address[MSB]	Address[MSB-1:16]	Page description	Address range
0	0	Distributor registers (GICD_) See Distributor register summary*.	`0x00000-0x0FFFF`
	1	Distributor registers for message-based SPIs (GICD_) See Distributor registers for message-based SPIs summary*.	`0x10000-0x1FFFF`
	2	Interrupt Translation Service control registers (GITS_) See ITS control register summary*.	`0x20000-0x2FFFF`
	3	Interrupt Translation Service register (GITS_TRANSLATER) See ITS translation register summary.	`0x30000-0x3FFFF`
	Otherwise	Reserved

When the MSB is HIGH as shown in Table 3.2, the set of pages contains the Redistributor pages in sequence. For example, the RDs that correspond to each core in the first cluster precede the RDs that correspond to each core in the second cluster.

Table 3.2. Upper half of address map

Address[MSB]	Address[MSB-1:17]	Address[16]	Page description
1	Global core number. This is a core number using the contiguous, linear representation as depicted in Figure 1.2.	0	Redistributor registers for control and physical LPIs (GICR_). See Redistributor registers for control and physical LPIs summary*
1	Redistributor registers for SGIs and PPIs (GICR_). See Redistributor registers for SGIs and PPIs summary*.
Values that do not correspond to a core number.	x	Reserved.

Address[MSB]

Address[MSB-1:17]

Address[16]

Page description

Global core number.

This is a core number using the contiguous, linear representation as depicted in Figure 1.2.

Redistributor registers for control and physical LPIs (GICR_*).

See Redistributor registers for control and physical LPIs summary

Redistributor registers for SGIs and PPIs (GICR_*).

See Redistributor registers for SGIs and PPIs summary.

Values that do not correspond to a core number.

Reserved.

For example, if there are four clusters, each with four cores, then there are 18 + max(1, 4) = 22 address bits, and the RD control registers for cluster 1, core 0 are at an offset 0x280000-0x28FFFF, with those for SGIs and PPIs at an offset of 0x29000-0x29FFFF.

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